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Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +09001/*
2 * Configuation settings for the Hitachi Solution Engine 7722
3 *
4 * Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +09007 */
8
9#ifndef __MS7722SE_H
10#define __MS7722SE_H
11
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090012#define CONFIG_SH 1
13#define CONFIG_SH4 1
14#define CONFIG_CPU_SH7722 1
15#define CONFIG_MS7722SE 1
16
17#define CONFIG_CMD_FLASH
Nobuhiro Iwamatsu57837582008-11-17 16:52:09 +090018#define CONFIG_CMD_JFFS2
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090019#define CONFIG_CMD_NET
Nobuhiro Iwamatsu57837582008-11-17 16:52:09 +090020#define CONFIG_CMD_NFS
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090021#define CONFIG_CMD_PING
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090022#define CONFIG_CMD_SDRAM
Nobuhiro Iwamatsu57837582008-11-17 16:52:09 +090023#define CONFIG_CMD_MEMORY
Mike Frysingerbdab39d2009-01-28 19:08:14 -050024#define CONFIG_CMD_SAVEENV
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090025
26#define CONFIG_BAUDRATE 115200
27#define CONFIG_BOOTDELAY 3
Wolfgang Denk53677ef2008-05-20 16:00:29 +020028#define CONFIG_BOOTARGS "console=ttySC0,115200 root=1f01"
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090029
30#define CONFIG_VERSION_VARIABLE
31#undef CONFIG_SHOW_BOOT_PROGRESS
32
33/* SMC9111 */
Ben Warren7194ab82009-10-04 22:37:03 -070034#define CONFIG_SMC91111
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090035#define CONFIG_SMC91111_BASE (0xB8000000)
36
37/* MEMORY */
38#define MS7722SE_SDRAM_BASE (0x8C000000)
39#define MS7722SE_FLASH_BASE_1 (0xA0000000)
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090040#define MS7722SE_FLASH_BANK_SIZE (8*1024 * 1024)
41
Nobuhiro Iwamatsu5c1877d2011-01-17 21:07:15 +090042#define CONFIG_SYS_TEXT_BASE 0x8FFC0000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020043#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_CBSIZE 256 /* Buffer size for input from the Console */
45#define CONFIG_SYS_PBSIZE 256 /* Buffer size for Console output */
46#define CONFIG_SYS_MAXARGS 16 /* max args accepted for monitor commands */
47#define CONFIG_SYS_BARGSIZE 512 /* Buffer size for Boot Arguments passed to kernel */
48#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } /* List of legal baudrate settings for this board */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090049
50/* SCIF */
Jean-Christophe PLAGNIOL-VILLARD6c58a032008-08-13 01:40:38 +020051#define CONFIG_SCIF_CONSOLE 1
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090052#define CONFIG_CONS_SCIF0 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020053#undef CONFIG_SYS_CONSOLE_INFO_QUIET /* Suppress display of console information at boot */
54#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
55#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090056
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020057#define CONFIG_SYS_MEMTEST_START (MS7722SE_SDRAM_BASE)
58#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090059
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#undef CONFIG_SYS_ALT_MEMTEST /* Enable alternate, more extensive, memory test */
61#undef CONFIG_SYS_MEMTEST_SCRATCH /* Scratch address used by the alternate memory test */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090062
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* Enable temporary baudrate change while serial download */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090064
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_SDRAM_BASE (MS7722SE_SDRAM_BASE)
66#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* maybe more, but if so u-boot doesn't know about it... */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090067
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024) /* default load address for scripts ?!? */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090069
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#define CONFIG_SYS_MONITOR_BASE (MS7722SE_FLASH_BASE_1) /* Address of u-boot image
Wolfgang Denk53677ef2008-05-20 16:00:29 +020071 in Flash (NOT run time address in SDRAM) ?!? */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_MONITOR_LEN (128 * 1024) /* */
73#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090075
76/* FLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +020078#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020079#undef CONFIG_SYS_FLASH_QUIET_TEST
80#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090081
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020082#define CONFIG_SYS_FLASH_BASE (MS7722SE_FLASH_BASE_1) /* Physical start address of Flash memory */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090083
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020084#define CONFIG_SYS_MAX_FLASH_SECT 150 /* Max number of sectors on each
Wolfgang Denk53677ef2008-05-20 16:00:29 +020085 Flash chip */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090086
87/* if you use all NOR Flash , you change dip-switch. Please see MS7722SE01 Manual. */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_MAX_FLASH_BANKS 2
89#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * MS7722SE_FLASH_BANK_SIZE), \
90 CONFIG_SYS_FLASH_BASE + (1 * MS7722SE_FLASH_BANK_SIZE), \
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090091 }
92
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020093#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) /* Timeout for Flash erase operations (in ms) */
94#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) /* Timeout for Flash write operations (in ms) */
95#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) /* Timeout for Flash set sector lock bit operations (in ms) */
96#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) /* Timeout for Flash clear lock bit operations (in ms) */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090097
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#undef CONFIG_SYS_FLASH_PROTECTION /* Use hardware flash sectors protection instead of U-Boot software protection */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +090099
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200100#undef CONFIG_SYS_DIRECT_FLASH_TFTP
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900101
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200102#define CONFIG_ENV_IS_IN_FLASH
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900103#define CONFIG_ENV_OVERWRITE 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200104#define CONFIG_ENV_SECT_SIZE (8 * 1024)
105#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + (1 * CONFIG_ENV_SECT_SIZE))
107#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) /* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200108#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + (2 * CONFIG_ENV_SECT_SIZE))
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900110
111/* Board Clock */
112#define CONFIG_SYS_CLK_FREQ 33333333
Nobuhiro Iwamatsu684a5012013-08-21 16:11:21 +0900113#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
114#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Jean-Christophe PLAGNIOL-VILLARDbe45c632009-06-04 12:06:48 +0200115#define CONFIG_SYS_TMU_CLK_DIV (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu6c0bbdc2007-09-23 02:31:13 +0900116
117#endif /* __MS7722SE_H */