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stroese13fdf8a2003-09-12 08:55:18 +00001/*
2 * (C) Copyright 2001-2003
3 * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405EP 1 /* This is a PPC405 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000037#define CONFIG_4xx 1 /* ...member of PPC4xx family */
stroesea20b27a2004-12-16 18:05:42 +000038#define CONFIG_HUB405 1 /* ...on a HUB405 board */
stroese13fdf8a2003-09-12 08:55:18 +000039
wdenkc837dcb2004-01-20 23:12:12 +000040#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
41#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
stroese13fdf8a2003-09-12 08:55:18 +000042
stroesea20b27a2004-12-16 18:05:42 +000043#define CONFIG_SYS_CLK_FREQ 33330000 /* external frequency to pll */
stroese13fdf8a2003-09-12 08:55:18 +000044
stroese47b1e3d2005-03-01 17:26:39 +000045#define CONFIG_BOARD_TYPES 1 /* support board types */
46
stroese13fdf8a2003-09-12 08:55:18 +000047#define CONFIG_BAUDRATE 9600
48#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
49
50#undef CONFIG_BOOTARGS
stroesea20b27a2004-12-16 18:05:42 +000051#undef CONFIG_BOOTCOMMAND
stroese13fdf8a2003-09-12 08:55:18 +000052
stroesea20b27a2004-12-16 18:05:42 +000053#define CONFIG_PREBOOT /* enable preboot variable */
54
stroese13fdf8a2003-09-12 08:55:18 +000055#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
56
57#define CONFIG_MII 1 /* MII PHY management */
wdenkc837dcb2004-01-20 23:12:12 +000058#define CONFIG_PHY_ADDR 0 /* PHY address */
stroesea20b27a2004-12-16 18:05:42 +000059#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
60
61#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
stroese13fdf8a2003-09-12 08:55:18 +000062
stroese13fdf8a2003-09-12 08:55:18 +000063
Jon Loeliger6c4f4da2007-07-08 10:09:35 -050064/*
Jon Loeliger11799432007-07-10 09:02:57 -050065 * BOOTP options
66 */
67#define CONFIG_BOOTP_BOOTFILESIZE
68#define CONFIG_BOOTP_BOOTPATH
69#define CONFIG_BOOTP_GATEWAY
70#define CONFIG_BOOTP_HOSTNAME
71
72
73/*
Jon Loeliger6c4f4da2007-07-08 10:09:35 -050074 * Command line configuration.
75 */
76#include <config_cmd_default.h>
77
78#define CONFIG_CMD_DHCP
79#define CONFIG_CMD_IRQ
80#define CONFIG_CMD_ELF
81#define CONFIG_CMD_NAND
82#define CONFIG_CMD_I2C
83#define CONFIG_CMD_MII
84#define CONFIG_CMD_PING
85#define CONFIG_CMD_EEPROM
86
stroese13fdf8a2003-09-12 08:55:18 +000087
wdenkc837dcb2004-01-20 23:12:12 +000088#undef CONFIG_WATCHDOG /* watchdog disabled */
stroese13fdf8a2003-09-12 08:55:18 +000089
wdenkc837dcb2004-01-20 23:12:12 +000090#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
stroese13fdf8a2003-09-12 08:55:18 +000091
92/*
93 * Miscellaneous configurable options
94 */
95#define CFG_LONGHELP /* undef to save memory */
96#define CFG_PROMPT "=> " /* Monitor Command Prompt */
97
98#undef CFG_HUSH_PARSER /* use "hush" command parser */
99#ifdef CFG_HUSH_PARSER
wdenkc837dcb2004-01-20 23:12:12 +0000100#define CFG_PROMPT_HUSH_PS2 "> "
stroese13fdf8a2003-09-12 08:55:18 +0000101#endif
102
Jon Loeliger6c4f4da2007-07-08 10:09:35 -0500103#if defined(CONFIG_CMD_KGDB)
wdenkc837dcb2004-01-20 23:12:12 +0000104#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000105#else
wdenkc837dcb2004-01-20 23:12:12 +0000106#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
stroese13fdf8a2003-09-12 08:55:18 +0000107#endif
108#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
109#define CFG_MAXARGS 16 /* max number of command args */
110#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
111
wdenkc837dcb2004-01-20 23:12:12 +0000112#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
stroese13fdf8a2003-09-12 08:55:18 +0000113
wdenkc837dcb2004-01-20 23:12:12 +0000114#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
stroese13fdf8a2003-09-12 08:55:18 +0000115
116#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
117#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
118
wdenkc837dcb2004-01-20 23:12:12 +0000119#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
120#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
121#define CFG_BASE_BAUD 691200
122#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */
stroese13fdf8a2003-09-12 08:55:18 +0000123
124/* The following table includes the supported baudrates */
wdenkc837dcb2004-01-20 23:12:12 +0000125#define CFG_BAUDRATE_TABLE \
stroese13fdf8a2003-09-12 08:55:18 +0000126 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
127 57600, 115200, 230400, 460800, 921600 }
128
129#define CFG_LOAD_ADDR 0x100000 /* default load address */
130#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
131
wdenkc837dcb2004-01-20 23:12:12 +0000132#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
stroese13fdf8a2003-09-12 08:55:18 +0000133
134#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
135
wdenkc837dcb2004-01-20 23:12:12 +0000136#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
stroese13fdf8a2003-09-12 08:55:18 +0000137
wdenkc837dcb2004-01-20 23:12:12 +0000138#define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */
stroese13fdf8a2003-09-12 08:55:18 +0000139
stroesea20b27a2004-12-16 18:05:42 +0000140/* Ethernet stuff */
141#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
142#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
wdenke2ffd592004-12-31 09:32:47 +0000143#define CONFIG_HAS_ETH1
stroesea20b27a2004-12-16 18:05:42 +0000144#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
145
stroese13fdf8a2003-09-12 08:55:18 +0000146/*-----------------------------------------------------------------------
147 * NAND-FLASH stuff
148 *-----------------------------------------------------------------------
149 */
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200150#define CFG_NAND_BASE_LIST { CFG_NAND_BASE }
151#define NAND_MAX_CHIPS 1
152#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
153#define NAND_BIG_DELAY_US 25
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100154
Matthias Fuchsbd84ee42007-07-09 10:10:06 +0200155#define CFG_NAND_CE (0x80000000 >> 1) /* our CE is GPIO1 */
156#define CFG_NAND_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
157#define CFG_NAND_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
158#define CFG_NAND_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
stroese13fdf8a2003-09-12 08:55:18 +0000159
Matthias Fuchsc750d2e2007-09-12 12:36:53 +0200160#define CFG_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */
161#define CFG_NAND_QUIET 1
stroesea20b27a2004-12-16 18:05:42 +0000162
stroese13fdf8a2003-09-12 08:55:18 +0000163/*-----------------------------------------------------------------------
164 * PCI stuff
165 *-----------------------------------------------------------------------
166 */
wdenkc837dcb2004-01-20 23:12:12 +0000167#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
168#define PCI_HOST_FORCE 1 /* configure as pci host */
169#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
stroese13fdf8a2003-09-12 08:55:18 +0000170
wdenkc837dcb2004-01-20 23:12:12 +0000171#undef CONFIG_PCI /* include pci support */
172#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */
173#undef CONFIG_PCI_PNP /* do pci plug-and-play */
174 /* resource configuration */
stroese13fdf8a2003-09-12 08:55:18 +0000175
wdenkc837dcb2004-01-20 23:12:12 +0000176#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
stroese13fdf8a2003-09-12 08:55:18 +0000177
wdenkc837dcb2004-01-20 23:12:12 +0000178#define CFG_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
179#define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */
180#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
181#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
182#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
183#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
184#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
185#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
186#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
stroese13fdf8a2003-09-12 08:55:18 +0000187
188/*-----------------------------------------------------------------------
189 * Start addresses for the final memory configuration
190 * (Set up by the startup code)
191 * Please note that CFG_SDRAM_BASE _must_ start at 0
192 */
193#define CFG_SDRAM_BASE 0x00000000
194#define CFG_FLASH_BASE 0xFFFC0000
195#define CFG_MONITOR_BASE CFG_FLASH_BASE
196#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
197#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
198
199/*
200 * For booting Linux, the board info and command line data
201 * have to be in the first 8 MB of memory, since this is
202 * the maximum mapped by the Linux kernel during initialization.
203 */
204#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
205/*-----------------------------------------------------------------------
206 * FLASH organization
207 */
208#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
209#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
210
211#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
212#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
213
wdenkc837dcb2004-01-20 23:12:12 +0000214#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
215#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
216#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
stroese13fdf8a2003-09-12 08:55:18 +0000217/*
218 * The following defines are added for buggy IOP480 byte interface.
219 * All other boards should use the standard values (CPCI405 etc.)
220 */
wdenkc837dcb2004-01-20 23:12:12 +0000221#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
222#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
223#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
stroese13fdf8a2003-09-12 08:55:18 +0000224
wdenkc837dcb2004-01-20 23:12:12 +0000225#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
stroese13fdf8a2003-09-12 08:55:18 +0000226
227#if 0 /* test-only */
wdenkc837dcb2004-01-20 23:12:12 +0000228#define CFG_JFFS2_FIRST_BANK 0 /* use for JFFS2 */
229#define CFG_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */
stroese13fdf8a2003-09-12 08:55:18 +0000230#endif
231
232/*-----------------------------------------------------------------------
233 * Environment Variable setup
234 */
Jean-Christophe PLAGNIOL-VILLARDbb1f8b42008-09-05 09:19:30 +0200235#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200236#define CONFIG_ENV_OFFSET 0x100 /* environment starts at the beginning of the EEPROM */
237#define CONFIG_ENV_SIZE 0x700 /* 2048 bytes may be used for env vars*/
stroese13fdf8a2003-09-12 08:55:18 +0000238 /* total size of a CAT24WC16 is 2048 bytes */
239
240#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
wdenkc837dcb2004-01-20 23:12:12 +0000241#define CFG_NVRAM_SIZE 242 /* NVRAM size */
stroese13fdf8a2003-09-12 08:55:18 +0000242
243/*-----------------------------------------------------------------------
244 * I2C EEPROM (CAT24WC16) for environment
245 */
246#define CONFIG_HARD_I2C /* I2c with hardware support */
247#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
248#define CFG_I2C_SLAVE 0x7F
249
250#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
wdenkc837dcb2004-01-20 23:12:12 +0000251#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
252/* mask of address bits that overflow into the "EEPROM chip address" */
stroese13fdf8a2003-09-12 08:55:18 +0000253#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
254#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
255 /* 16 byte page write mode using*/
wdenkc837dcb2004-01-20 23:12:12 +0000256 /* last 4 bits of the address */
stroese13fdf8a2003-09-12 08:55:18 +0000257#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
stroese13fdf8a2003-09-12 08:55:18 +0000258
stroese13fdf8a2003-09-12 08:55:18 +0000259/*
260 * Init Memory Controller:
261 *
262 * BR0/1 and OR0/1 (FLASH)
263 */
264
265#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
266
267/*-----------------------------------------------------------------------
268 * External Bus Controller (EBC) Setup
269 */
270
wdenkc837dcb2004-01-20 23:12:12 +0000271/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
272#define CFG_EBC_PB0AP 0x92015480
273/*#define CFG_EBC_PB0AP 0x08055880 /XXX* TWT=16,CSN=1,OEN=1,WBN=1,WBF=1,TH=4,SOR=1 */
274#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
stroese13fdf8a2003-09-12 08:55:18 +0000275
wdenkc837dcb2004-01-20 23:12:12 +0000276/* Memory Bank 1 (Flash Bank 1, NAND-FLASH) initialization */
277#define CFG_EBC_PB1AP 0x92015480
278#define CFG_EBC_PB1CR 0xF4018000 /* BAS=0xF40,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000279
wdenkc837dcb2004-01-20 23:12:12 +0000280/* Memory Bank 2 (8 Bit Peripheral: UART) initialization */
stroese13fdf8a2003-09-12 08:55:18 +0000281#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000282#define CFG_EBC_PB2AP 0x010053C0 /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
283#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000284#else
wdenkc837dcb2004-01-20 23:12:12 +0000285#define CFG_EBC_PB2AP 0x92015480
286#define CFG_EBC_PB2CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
stroese13fdf8a2003-09-12 08:55:18 +0000287#endif
288
wdenkc837dcb2004-01-20 23:12:12 +0000289#define DUART0_BA 0xF0000000 /* DUART Base Address */
290#define DUART1_BA 0xF0000008 /* DUART Base Address */
291#define DUART2_BA 0xF0000010 /* DUART Base Address */
292#define DUART3_BA 0xF0000018 /* DUART Base Address */
293#define CFG_NAND_BASE 0xF4000000
stroese13fdf8a2003-09-12 08:55:18 +0000294
295/*-----------------------------------------------------------------------
296 * FPGA stuff
297 */
wdenkc837dcb2004-01-20 23:12:12 +0000298#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
299#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
stroese13fdf8a2003-09-12 08:55:18 +0000300
301/* FPGA program pin configuration */
wdenkc837dcb2004-01-20 23:12:12 +0000302#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
303#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
304#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
305#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
306#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
stroese13fdf8a2003-09-12 08:55:18 +0000307
308/*-----------------------------------------------------------------------
309 * Definitions for initial stack pointer and data area (in data cache)
310 */
311/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
wdenkc837dcb2004-01-20 23:12:12 +0000312#define CFG_TEMP_STACK_OCM 1
stroese13fdf8a2003-09-12 08:55:18 +0000313
314/* On Chip Memory location */
315#define CFG_OCM_DATA_ADDR 0xF8000000
316#define CFG_OCM_DATA_SIZE 0x1000
317#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
318#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
319
320#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
321#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
wdenkc837dcb2004-01-20 23:12:12 +0000322#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
stroese13fdf8a2003-09-12 08:55:18 +0000323
324/*-----------------------------------------------------------------------
325 * Definitions for GPIO setup (PPC405EP specific)
326 *
wdenkc837dcb2004-01-20 23:12:12 +0000327 * GPIO0[0] - External Bus Controller BLAST output
328 * GPIO0[1-9] - Instruction trace outputs -> GPIO
stroese13fdf8a2003-09-12 08:55:18 +0000329 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
330 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
331 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
332 * GPIO0[24-27] - UART0 control signal inputs/outputs
333 * GPIO0[28-29] - UART1 data signal input/output
334 * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
335 */
wdenkc837dcb2004-01-20 23:12:12 +0000336#define CFG_GPIO0_OSRH 0x40000550
337#define CFG_GPIO0_OSRL 0x00000110
338#define CFG_GPIO0_ISR1H 0x00000000
339#define CFG_GPIO0_ISR1L 0x15555445
340#define CFG_GPIO0_TSRH 0x00000000
341#define CFG_GPIO0_TSRL 0x00000000
342#define CFG_GPIO0_TCR 0xF7FE0014
stroese13fdf8a2003-09-12 08:55:18 +0000343
stroesea20b27a2004-12-16 18:05:42 +0000344#define CFG_DUART_RST (0x80000000 >> 14)
345#define CFG_UART2_RS232 (0x80000000 >> 5)
346#define CFG_UART3_RS232 (0x80000000 >> 6)
347#define CFG_UART4_RS232 (0x80000000 >> 7)
348#define CFG_UART5_RS232 (0x80000000 >> 8)
stroese13fdf8a2003-09-12 08:55:18 +0000349
350/*
351 * Internal Definitions
352 *
353 * Boot Flags
354 */
355#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
356#define BOOTFLAG_WARM 0x02 /* Software reboot */
357
358/*
359 * Default speed selection (cpu_plb_opb_ebc) in mhz.
360 * This value will be set if iic boot eprom is disabled.
361 */
362#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000363#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
364#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000365#endif
366#if 0
wdenkc837dcb2004-01-20 23:12:12 +0000367#define PLLMR0_DEFAULT PLLMR0_200_100_50_33
368#define PLLMR1_DEFAULT PLLMR1_200_100_50_33
stroese13fdf8a2003-09-12 08:55:18 +0000369#endif
370#if 1
wdenkc837dcb2004-01-20 23:12:12 +0000371#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
372#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
stroese13fdf8a2003-09-12 08:55:18 +0000373#endif
374
375#endif /* __CONFIG_H */