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wdenk0608e042004-03-25 19:29:38 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2000-2005
wdenk0608e042004-03-25 19:29:38 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * board/config.h - configuration options, board specific
27 * Derived from ../tqm8xx/tqm8xx.c
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC859T 1 /* This is a MPC859T CPU */
39#define CONFIG_KUP4X 1 /* ...on a KUP4X module */
40
41#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
44#define CONFIG_BAUDRATE 115200 /* console baudrate */
45#if 0
46#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47#else
48#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */
49#endif
50
wdenk0608e042004-03-25 19:29:38 +000051#define CONFIG_BOARD_TYPES 1 /* support board types */
52
53#define CFG_8XX_FACT 8 /* Multiply by 8 */
54#define CFG_8XX_XIN 16000000 /* 16 MHz in */
55
56
57#define MPC8XX_HZ ((CFG_8XX_XIN) * (CFG_8XX_FACT))
58
59/* should ALWAYS define this, measure_gclk in speed.c is unreliable */
60/* in general, we always know this for FADS+new ADS anyway */
61#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
62
63
64#undef CONFIG_BOOTARGS
65
66
67#define CONFIG_EXTRA_ENV_SETTINGS \
68"slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;" \
69 "run addhw;diskboot 200000 0:1;bootm 200000\0" \
wdenk02b11f82004-05-12 22:54:36 +000070"usb_boot=setenv bootargs root=/dev/sda2 ip=off;\
71 run addhw; sleep 2; usb reset; usb scan; usbboot 200000 0:1;\
72 usb stop; bootm 200000\0" \
wdenk0608e042004-03-25 19:29:38 +000073"nfs_boot=dhcp;run nfsargs addip addhw;bootm 200000\0" \
74"panic_boot=echo No Bootdevice !!! reset\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010075"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0" \
wdenk0608e042004-03-25 19:29:38 +000076"ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010077"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}" \
78 ":${netmask}:${hostname}:${netdev}:off\0" \
79"addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0" \
wdenk0608e042004-03-25 19:29:38 +000080"netdev=eth0\0" \
81"silent=1\0" \
82"load=tftp 200000 bootloader-4x.bitmap;tftp 100000 bootloader-4x.bin\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010083"update=protect off 1:0-5;era 1:0-5;cp.b 100000 40000000 ${filesize};" \
wdenk0608e042004-03-25 19:29:38 +000084 "cp.b 200000 40040000 14000\0"
85
86#define CONFIG_BOOTCOMMAND \
wdenk02b11f82004-05-12 22:54:36 +000087 "run usb_boot;run_slot_a_boot;run nfs_boot;run panic_boot"
wdenk0608e042004-03-25 19:29:38 +000088
89
90#define CONFIG_MISC_INIT_R 1
91#define CONFIG_MISC_INIT_F 1
92
93#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
94#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
95
wdenk02b11f82004-05-12 22:54:36 +000096#define CONFIG_WATCHDOG 1 /* watchdog enabled */
wdenk0608e042004-03-25 19:29:38 +000097
98#define CONFIG_STATUS_LED 1 /* Status LED enabled */
99
100#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
101
Jon Loeliger7be044e2007-07-09 21:24:19 -0500102/*
103 * BOOTP options
104 */
105#define CONFIG_BOOTP_SUBNETMASK
106#define CONFIG_BOOTP_GATEWAY
107#define CONFIG_BOOTP_HOSTNAME
108#define CONFIG_BOOTP_BOOTPATH
109#define CONFIG_BOOTP_BOOTFILESIZE
110
wdenk0608e042004-03-25 19:29:38 +0000111
112#define CONFIG_MAC_PARTITION
113#define CONFIG_DOS_PARTITION
114
wdenk02b11f82004-05-12 22:54:36 +0000115/*
116 * enable I2C and select the hardware/software driver
117 */
118#undef CONFIG_HARD_I2C /* I2C with hardware support */
119#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
wdenk0608e042004-03-25 19:29:38 +0000120
wdenk02b11f82004-05-12 22:54:36 +0000121#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */
122#define CFG_I2C_SLAVE 0xFE
123
124#ifdef CONFIG_SOFT_I2C
125/*
126 * Software (bit-bang) I2C driver configuration
127 */
128#define PB_SCL 0x00000020 /* PB 26 */
129#define PB_SDA 0x00000010 /* PB 27 */
130
131#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
132#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
133#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
134#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
135#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
136 else immr->im_cpm.cp_pbdat &= ~PB_SDA
137#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
138 else immr->im_cpm.cp_pbdat &= ~PB_SCL
139#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
140#endif /* CONFIG_SOFT_I2C */
141
142
143/*-----------------------------------------------------------------------
144 * I2C Configuration
145 */
146
147#define CFG_I2C_PICIO_ADDR 0x21 /* PCF8574 IO Expander */
148#define CFG_I2C_RTC_ADDR 0x51 /* PCF8563 RTC */
149
150
151/* List of I2C addresses to be verified by POST */
152
153#define I2C_ADDR_LIST {CFG_I2C_PICIO_ADDR, \
154 CFG_I2C_RTC_ADDR, \
155 }
156
157
158#define CONFIG_RTC_PCF8563 /* use Philips PCF8563 RTC */
159
160#define CFG_DISCOVER_PHY
Marian Balakowicz63ff0042005-10-28 22:30:33 +0200161#define CONFIG_MII
wdenk02b11f82004-05-12 22:54:36 +0000162
163#if 0
164#define CONFIG_ETHADDR 00:0B:64:80:00:00 /* our OUI from IEEE */
165#endif
wdenk0608e042004-03-25 19:29:38 +0000166#undef CONFIG_KUP4K_LOGO
167
168/* Define to allow the user to overwrite serial and ethaddr */
169#define CONFIG_ENV_OVERWRITE
170
wdenk02b11f82004-05-12 22:54:36 +0000171
172#if 1
173/* POST support */
174
175#define CONFIG_POST (CFG_POST_CPU | \
176 CFG_POST_RTC | \
177 CFG_POST_I2C)
wdenk02b11f82004-05-12 22:54:36 +0000178#endif
179
wdenk0608e042004-03-25 19:29:38 +0000180
Jon Loeliger348f2582007-07-08 13:46:18 -0500181/*
182 * Command line configuration.
183 */
184#include <config_cmd_default.h>
185
186#define CONFIG_CMD_DATE
187#define CONFIG_CMD_DHCP
188#define CONFIG_CMD_FAT
189#define CONFIG_CMD_I2C
190#define CONFIG_CMD_IDE
191#define CONFIG_CMD_NFS
Jon Loeliger348f2582007-07-08 13:46:18 -0500192#define CONFIG_CMD_SNTP
193#define CONFIG_CMD_USB
194
Jon Loeligeraf075ee2007-07-08 17:02:01 -0500195#ifdef CONFIG_POST
196 #define CONFIG_CMD_DIAG
197#endif
wdenk0608e042004-03-25 19:29:38 +0000198
199/*
200 * Miscellaneous configurable options
201 */
202#define CFG_LONGHELP /* undef to save memory */
203#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500204#if defined(CONFIG_CMD_KGDB)
wdenk0608e042004-03-25 19:29:38 +0000205#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
206#else
207#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
208#endif
209#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
210#define CFG_MAXARGS 16 /* max number of command args */
211#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
212
213#define CFG_MEMTEST_START 0x000400000 /* memtest works on */
214#define CFG_MEMTEST_END 0x003C00000 /* 4 ... 60 MB in DRAM */
215#define CFG_LOAD_ADDR 0x200000 /* default load address */
216
217#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
218
219#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
220
221#define CFG_CONSOLE_INFO_QUIET 1
222
223/*
224 * Low Level Configuration Settings
225 * (address mappings, register initial values, etc.)
226 * You should know what you are doing if you make changes here.
227 */
228/*-----------------------------------------------------------------------
229 * Internal Memory Mapped Register
230 */
231#define CFG_IMMR 0xFFF00000
232
233/*-----------------------------------------------------------------------
234 * Definitions for initial stack pointer and data area (in DPRAM)
235 */
236#define CFG_INIT_RAM_ADDR CFG_IMMR
237#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
238#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
239#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
240#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
241
242/*-----------------------------------------------------------------------
243 * Start addresses for the final memory configuration
244 * (Set up by the startup code)
245 * Please note that CFG_SDRAM_BASE _must_ start at 0
246 */
247#define CFG_SDRAM_BASE 0x00000000
248#define CFG_FLASH_BASE 0x40000000
249#define CFG_MONITOR_LEN (192 << 10) /* Reserve 256 kB for Monitor */
250#define CFG_MONITOR_BASE CFG_FLASH_BASE
251#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
252
253/*
254 * For booting Linux, the board info and command line data
255 * have to be in the first 8 MB of memory, since this is
256 * the maximum mapped by the Linux kernel during initialization.
257 */
258#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
259
260/*-----------------------------------------------------------------------
261 * FLASH organization
262 */
263#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
264#define CFG_MAX_FLASH_SECT 19 /* max number of sectors on one chip */
265
266#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
267#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
268
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200269#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200270#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
271#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */
272#define CONFIG_ENV_SECT_SIZE 0x10000
wdenk0608e042004-03-25 19:29:38 +0000273
274/* Address and size of Redundant Environment Sector */
275#if 0
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200276#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
277#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenk0608e042004-03-25 19:29:38 +0000278#endif
279/*-----------------------------------------------------------------------
280 * Hardware Information Block
281 */
wdenk02b11f82004-05-12 22:54:36 +0000282#if 1
283#define CFG_HWINFO_OFFSET 0x000F0000 /* offset of HW Info block */
284#define CFG_HWINFO_SIZE 0x00000100 /* size of HW Info block */
285#define CFG_HWINFO_MAGIC 0x4B26500D /* 'K&P<CR>' */
wdenk0608e042004-03-25 19:29:38 +0000286#endif
287/*-----------------------------------------------------------------------
288 * Cache Configuration
289 */
290#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger348f2582007-07-08 13:46:18 -0500291#if defined(CONFIG_CMD_KGDB)
wdenk0608e042004-03-25 19:29:38 +0000292#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
293#endif
294
295/*-----------------------------------------------------------------------
296 * SYPCR - System Protection Control 11-9
297 * SYPCR can only be written once after reset!
298 *-----------------------------------------------------------------------
299 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
300 */
wdenk02b11f82004-05-12 22:54:36 +0000301#if 0 && defined(CONFIG_WATCHDOG) /* KUP uses external TPS3705 WD */
wdenk0608e042004-03-25 19:29:38 +0000302#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
303 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
304#else
305#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
306#endif
307
308/*-----------------------------------------------------------------------
309 * SIUMCR - SIU Module Configuration 11-6
310 *-----------------------------------------------------------------------
311 * PCMCIA config., multi-function pin tri-state
312 */
313#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
314
315/*-----------------------------------------------------------------------
316 * TBSCR - Time Base Status and Control 11-26
317 *-----------------------------------------------------------------------
318 * Clear Reference Interrupt Status, Timebase freezing enabled
319 */
320#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
321
322
323/*-----------------------------------------------------------------------
324 * PISCR - Periodic Interrupt Status and Control 11-31
325 *-----------------------------------------------------------------------
326 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
327 */
328#define CFG_PISCR (PISCR_PS | PISCR_PITF)
329
330
331/*-----------------------------------------------------------------------
332 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
333 *-----------------------------------------------------------------------
334 * set the PLL, the low-power modes and the reset control (15-29)
335 */
336#define CFG_PLPRCR ((CFG_8XX_FACT << PLPRCR_MFI_SHIFT) | \
337 PLPRCR_SPLSS | PLPRCR_TEXPS)
338
339
340/*-----------------------------------------------------------------------
341 * SCCR - System Clock and reset Control Register 15-27
342 *-----------------------------------------------------------------------
343 * Set clock output, timebase and RTC source and divider,
344 * power management and some other internal clocks
345 */
346#define SCCR_MASK SCCR_EBDF00
347#define CFG_SCCR (SCCR_TBS | SCCR_EBDF01 | \
348 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
349 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
350 SCCR_DFALCD00)
351
352/*-----------------------------------------------------------------------
353 * PCMCIA stuff
354 *-----------------------------------------------------------------------
355 *
356 */
357
358/* KUP4K use both slots, SLOT_A as "primary". */
359#define CONFIG_PCMCIA_SLOT_A 1
360
361#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
362#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
363#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
364#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
365#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
366#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
367#define CFG_PCMCIA_IO_ADDR (0xEC000000)
368#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
369
370#define PCMCIA_SOCKETS_NO 1
371#define PCMCIA_MEM_WIN_NO 8
372/*-----------------------------------------------------------------------
373 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
374 *-----------------------------------------------------------------------
375 */
376
377#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
378
379#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
380#define CONFIG_IDE_LED 1 /* LED for ide supported */
381#undef CONFIG_IDE_RESET /* reset for ide not supported */
382
383#define CFG_IDE_MAXBUS 1
384#define CFG_IDE_MAXDEVICE 2
385
386#define CFG_ATA_IDE0_OFFSET 0x0000
387
388#define CFG_ATA_IDE1_OFFSET (4 * CFG_PCMCIA_MEM_SIZE)
389
390#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
391
392/* Offset for data I/O */
393#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
394
395/* Offset for normal register accesses */
396#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
397
398/* Offset for alternate registers */
399#define CFG_ATA_ALT_OFFSET 0x0100
400
401
402/*-----------------------------------------------------------------------
403 *
404 *-----------------------------------------------------------------------
405 *
406 */
407#define CFG_DER 0
408
409/*
410 * Init Memory Controller:
411 *
412 * BR0/1 and OR0/1 (FLASH)
413 */
414#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
415
416/* used to re-map FLASH both when starting from SRAM or FLASH:
417 * restrict access enough to keep SRAM working (if any)
418 * but not too much to meddle with FLASH accesses
419 */
420#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
421#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
422
423/*
424 * FLASH timing:
425 */
426#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
427 OR_SCY_2_CLK | OR_EHTR | OR_BI)
428
429#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
430#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
431#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
432
433
434/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
435#define CFG_OR_TIMING_SDRAM 0x00000A00
436
437
438#define CFG_MPTPR 0x400
439
440/*
441 * MAMR settings for SDRAM
442 */
443#define CFG_MAMR 0x80802114
444
445
446/*
447 * Internal Definitions
448 *
449 * Boot Flags
450 */
451#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
452#define BOOTFLAG_WARM 0x02 /* Software reboot */
453
454
455#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */
456#if 0
Stefan Roesef2302d42008-08-06 14:05:38 +0200457#define CONFIG_AUTOBOOT_PROMPT \
458 "Boote in %d Sekunden - stop mit \"2\"\n", bootdelay
wdenk0608e042004-03-25 19:29:38 +0000459#endif
460#define CONFIG_AUTOBOOT_STOP_STR "." /* easy to stop for now */
461#define CONFIG_SILENT_CONSOLE 1
462
wdenk5cf91d62004-04-23 20:32:05 +0000463#define CONFIG_USB_STORAGE 1
464#define CONFIG_USB_SL811HS 1
465
wdenk0608e042004-03-25 19:29:38 +0000466#endif /* __CONFIG_H */