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Heiko Schocher381e4e62008-01-11 01:12:06 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC866 1 /* This is a MPC866 CPU */
37#define CONFIG_MGSUVD 1 /* ...on a mgsuvd board */
38
Heiko Schocher82afabf2008-03-07 08:15:28 +010039/* Do boardspecific init */
40#define CONFIG_BOARD_EARLY_INIT_R 1
41
Heiko Schocher381e4e62008-01-11 01:12:06 +010042#define CONFIG_8xx_GCLK_FREQ 66000000
43
44#define CFG_SMC_UCODE_PATCH 1 /* Relocate SMC1 */
45#define CFG_SMC_DPMEM_OFFSET 0x1fc0
46#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
47
48#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
49
50#define CONFIG_BOOTCOUNT_LIMIT
51
52#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
53
54#define CONFIG_BOARD_TYPES 1 /* support board types */
55
56#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010057 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Heiko Schocher381e4e62008-01-11 01:12:06 +010058 "echo"
59
60#undef CONFIG_BOOTARGS
61
Detlev Zundelc61e0332008-04-03 14:18:48 +020062#define CONFIG_EXTRA_ENV_SETTINGS \
63 "netdev=eth0\0" \
Detlev Zundelf3085722008-04-03 14:18:47 +020064 "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \
Detlev Zundelc61e0332008-04-03 14:18:48 +020065 "nfsargs=setenv bootargs root=/dev/nfs rw " \
66 "nfsroot=${serverip}:${rootpath}\0" \
67 "ramargs=setenv bootargs root=/dev/ram rw\0" \
68 "addip=setenv bootargs ${bootargs} " \
69 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
70 ":${hostname}:${netdev}:off panic=1\0" \
71 "flash_nfs=run nfsargs addip;" \
72 "bootm ${kernel_addr}\0" \
73 "flash_self=run ramargs addip;" \
74 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
75 "net_nfs=tftp ${kernel_addr} ${bootfile}; " \
76 "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \
77 "bootm ${kernel_addr} - ${fdt_addr}\0" \
78 "rootpath=/opt/eldk/ppc_8xx\0" \
79 "bootfile=/tftpboot/mgsuvd/uImage\0" \
80 "fdt_addr=400000\0" \
81 "kernel_addr=200000\0" \
82 "fdt_file=/tftpboot/mgsuvd/mgsuvd.dtb\0" \
83 "load=tftp 200000 ${u-boot}\0" \
84 "update=protect off f0000000 +${filesize};" \
85 "erase f0000000 +${filesize};" \
86 "cp.b 200000 f0000000 ${filesize};" \
87 "protect on f0000000 +${filesize}\0" \
Heiko Schocher381e4e62008-01-11 01:12:06 +010088 ""
89#define CONFIG_BOOTCOMMAND "run flash_self"
90
91#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
92#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
93
94#undef CONFIG_WATCHDOG /* watchdog disabled */
95
96/*
97 * BOOTP options
98 */
99#define CONFIG_BOOTP_SUBNETMASK
100#define CONFIG_BOOTP_GATEWAY
101#define CONFIG_BOOTP_HOSTNAME
102#define CONFIG_BOOTP_BOOTPATH
103#define CONFIG_BOOTP_BOOTFILESIZE
104
105#undef CONFIG_RTC_MPC8xx /* MPC866 does not support RTC */
106
107#define CONFIG_TIMESTAMP /* but print image timestmps */
108
109/*
110 * Command line configuration.
111 */
112#include <config_cmd_default.h>
113
114#define CONFIG_CMD_ASKENV
115#define CONFIG_CMD_DHCP
Heiko Schochere5e4edd2008-10-15 09:38:07 +0200116#define CONFIG_CMD_DTT
Heiko Schocherf2202452008-10-15 09:36:33 +0200117#define CONFIG_CMD_EEPROM
Heiko Schocher9661bf92008-10-15 09:36:03 +0200118#define CONFIG_CMD_I2C
Heiko Schocher381e4e62008-01-11 01:12:06 +0100119#define CONFIG_CMD_NFS
120#define CONFIG_CMD_PING
121
122/*
123 * Miscellaneous configurable options
124 */
125#define CFG_LONGHELP /* undef to save memory */
126#define CFG_PROMPT "=> " /* Monitor Command Prompt */
127
128#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
129#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
130#ifdef CFG_HUSH_PARSER
131#define CFG_PROMPT_HUSH_PS2 "> "
Heiko Schocher8f64da72008-10-15 09:41:00 +0200132#define CONFIG_HUSH_INIT_VAR 1
Heiko Schocher381e4e62008-01-11 01:12:06 +0100133#endif
134
135#if defined(CONFIG_CMD_KGDB)
136#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
137#else
138#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
139#endif
140#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
141#define CFG_MAXARGS 16 /* max number of command args */
142#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
143
144#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
145#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
146
147#define CFG_LOAD_ADDR 0x100000 /* default load address */
148
149#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
150
151#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
152
153/*
154 * Low Level Configuration Settings
155 * (address mappings, register initial values, etc.)
156 * You should know what you are doing if you make changes here.
157 */
158/*-----------------------------------------------------------------------
159 * Internal Memory Mapped Register
160 */
161#define CFG_IMMR 0xFFF00000
162
163/*-----------------------------------------------------------------------
164 * Definitions for initial stack pointer and data area (in DPRAM)
165 */
166#define CFG_INIT_RAM_ADDR CFG_IMMR
167#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
168#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
169#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
170#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
171
172/*-----------------------------------------------------------------------
173 * Start addresses for the final memory configuration
174 * (Set up by the startup code)
175 * Please note that CFG_SDRAM_BASE _must_ start at 0
176 */
177#define CFG_SDRAM_BASE 0x00000000
178#define CFG_FLASH_BASE 0xf0000000
179#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
180#define CFG_MONITOR_BASE CFG_FLASH_BASE
181#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
182
183/*
184 * For booting Linux, the board info and command line data
185 * have to be in the first 8 MB of memory, since this is
186 * the maximum mapped by the Linux kernel during initialization.
187 */
188#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
189
190/*-----------------------------------------------------------------------
191 * FLASH organization
192 */
193#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
194#define CFG_FLASH_SIZE 32
195#define CFG_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200196#define CONFIG_FLASH_CFI_DRIVER
Heiko Schocher381e4e62008-01-11 01:12:06 +0100197#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
198
199
200#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
201#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
202
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200203#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200204#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */
205#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment Sector */
206#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */
Heiko Schocher381e4e62008-01-11 01:12:06 +0100207
208/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200209#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
210#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Heiko Schocher381e4e62008-01-11 01:12:06 +0100211
212#define CFG_USE_PPCENV /* Environment embedded in sect .ppcenv */
213
214/*-----------------------------------------------------------------------
215 * Cache Configuration
216 */
217#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
218#if defined(CONFIG_CMD_KGDB)
219#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
220#endif
221
222/*-----------------------------------------------------------------------
223 * SYPCR - System Protection Control 11-9
224 * SYPCR can only be written once after reset!
225 *-----------------------------------------------------------------------
226 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
227 */
228#define CFG_SYPCR 0xffffff89
229
230/*-----------------------------------------------------------------------
231 * SIUMCR - SIU Module Configuration 11-6
232 *-----------------------------------------------------------------------
233 */
234#define CFG_SIUMCR 0x00610480
235
236/*-----------------------------------------------------------------------
237 * TBSCR - Time Base Status and Control 11-26
238 *-----------------------------------------------------------------------
239 * Clear Reference Interrupt Status, Timebase freezing enabled
240 */
241#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
242
243/*-----------------------------------------------------------------------
244 * PISCR - Periodic Interrupt Status and Control 11-31
245 *-----------------------------------------------------------------------
246 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
247 */
248#define CFG_PISCR (PISCR_PS | PISCR_PITF)
249
250/*-----------------------------------------------------------------------
251 * SCCR - System Clock and reset Control Register 15-27
252 *-----------------------------------------------------------------------
253 * Set clock output, timebase and RTC source and divider,
254 * power management and some other internal clocks
255 */
256#define SCCR_MASK 0x01800000
257#define CFG_SCCR 0x01800000
258
259#define CFG_DER 0
260
261/*
262 * Init Memory Controller:
263 *
264 * BR0/1 and OR0/1 (FLASH)
265 */
266
267#define FLASH_BASE0_PRELIM 0xf0000000 /* FLASH bank #0 */
268
269/* used to re-map FLASH both when starting from SRAM or FLASH:
270 * restrict access enough to keep SRAM working (if any)
271 * but not too much to meddle with FLASH accesses
272 */
273#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
274#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
275
276/*
277 * FLASH timing: Default value of OR0 after reset
278 */
279#define CFG_OR0_PRELIM 0xfe000954
280#define CFG_BR0_PRELIM 0xf0000401
281
282/*
283 * BR1 and OR1 (SDRAM)
284 *
285 */
286#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
287#define SDRAM_MAX_SIZE (64 << 20) /* max 64 MB per bank */
288
289/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
290#define CFG_OR_TIMING_SDRAM 0x00000A00
291
292#define CFG_OR1_PRELIM 0xfc000800
293#define CFG_BR1_PRELIM (0x000000C0 | 0x01)
294
295#define CFG_MPTPR 0x0200
296/* PTB=16, AMB=001, FIXME 1 RAS precharge cycles, 1 READ loop cycle (not used),
297 1 Write loop Cycle (not used), 1 Timer Loop Cycle */
298#define CFG_MBMR 0x10964111
299#define CFG_MAR 0x00000088
300
301/*
302 * 4096 Rows from SDRAM example configuration
303 * 1000 factor s -> ms
304 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration
305 * 4 Number of refresh cycles per period
306 * 64 Refresh cycle in ms per number of rows
307 */
308#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64))
Heiko Schocher82afabf2008-03-07 08:15:28 +0100309
310/* GPIO/PIGGY on CS3 initialization values
311*/
312#define CFG_PIGGY_BASE (0x30000000)
313#define CFG_OR3_PRELIM (0xfe000d24)
314#define CFG_BR3_PRELIM (0x30000401)
Heiko Schocher381e4e62008-01-11 01:12:06 +0100315
316/*
317 * Internal Definitions
318 *
319 * Boot Flags
320 */
321#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
322#define BOOTFLAG_WARM 0x02 /* Software reboot */
323
324#define CONFIG_SCC3_ENET
325#define CONFIG_ETHPRIME "SCC ETHERNET"
326#define CONFIG_HAS_ETH0
327
328/* pass open firmware flat tree */
329#define CONFIG_OF_LIBFDT 1
330#define CONFIG_OF_BOARD_SETUP 1
331
332#define OF_CPU "PowerPC,866@0"
Heiko Schocher82afabf2008-03-07 08:15:28 +0100333#define OF_SOC "soc@fff00000"
Heiko Schocher381e4e62008-01-11 01:12:06 +0100334#define OF_TBCLK (bd->bi_busfreq / 4)
335#define OF_STDOUT_PATH "/soc/cpm/serial@a80"
336
Heiko Schocher9661bf92008-10-15 09:36:03 +0200337/* enable I2C and select the hardware/software driver */
338#undef CONFIG_HARD_I2C /* I2C with hardware support */
339#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
340#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
341#define CFG_I2C_SLAVE 0x7F
342#define I2C_SOFT_DECLARATIONS
343
344/*
345 * Software (bit-bang) I2C driver configuration
346 */
347#define I2C_BASE_DIR (CFG_PIGGY_BASE + 0x04)
348#define I2C_BASE_PORT (CFG_PIGGY_BASE + 0x09)
349
350#define SDA_BIT 0x40
351#define SCL_BIT 0x80
352#define SDA_CONF 0x1000
353#define SCL_CONF 0x2000
354
355#define I2C_ACTIVE do {} while (0)
356#define I2C_TRISTATE do {} while (0)
357#define I2C_READ i2c_soft_read_pin ()
358#define I2C_SDA(bit) if(bit) { \
359 *(unsigned short *)(I2C_BASE_DIR) &= ~SDA_CONF; \
360 } \
361 else { \
362 *(unsigned char *)(I2C_BASE_PORT) &= ~SDA_BIT; \
363 *(unsigned short *)(I2C_BASE_DIR) |= SDA_CONF; \
364 }
365#define I2C_SCL(bit) if(bit) { \
366 *(unsigned short *)(I2C_BASE_DIR) &= ~SCL_CONF; \
367 } \
368 else { \
369 *(unsigned char *)(I2C_BASE_PORT) &= ~SCL_BIT; \
370 *(unsigned short *)(I2C_BASE_DIR) |= SCL_CONF; \
371 }
372#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */
373
374#define CONFIG_I2C_MULTI_BUS 1
375#define CONFIG_I2C_CMD_TREE 1
376#define CFG_MAX_I2C_BUS 2
Heiko Schocherc2485362008-10-15 09:39:08 +0200377#define CFG_I2C_INIT_BOARD 1
Heiko Schocher67b23a32008-10-15 09:39:47 +0200378#define CONFIG_I2C_MUX 1
Heiko Schocher9661bf92008-10-15 09:36:03 +0200379
Heiko Schocherf2202452008-10-15 09:36:33 +0200380/* EEprom support */
381#define CFG_I2C_EEPROM_ADDR_LEN 1
382#define CFG_I2C_MULTI_EEPROMS 1
383#define CFG_EEPROM_PAGE_WRITE_ENABLE
384#define CFG_EEPROM_PAGE_WRITE_BITS 3
385#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
Heiko Schocher9661bf92008-10-15 09:36:03 +0200386
Heiko Schocher8f64da72008-10-15 09:41:00 +0200387/* Support the IVM EEprom */
388#define CFG_IVM_EEPROM_ADR 0x50
389#define CFG_IVM_EEPROM_MAX_LEN 0x400
390#define CFG_IVM_EEPROM_PAGE_LEN 0x100
391
Heiko Schochere5e4edd2008-10-15 09:38:07 +0200392/* I2C SYSMON (LM75, AD7414 is almost compatible) */
393#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
394#define CONFIG_DTT_SENSORS {0, 2, 4, 6} /* Sensor addresses */
395#define CFG_DTT_MAX_TEMP 70
396#define CFG_DTT_LOW_TEMP -30
397#define CFG_DTT_HYSTERESIS 3
398#define CFG_DTT_BUS_NUM (CFG_MAX_I2C_BUS)
399
Heiko Schocher381e4e62008-01-11 01:12:06 +0100400#endif /* __CONFIG_H */