blob: 96b4c25726327600e85b6eec02372ebb1eb3ca54 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Patrice Chotarde23b19f2018-01-18 13:39:32 +01002/*
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
Patrice Chotard0f8106f2020-12-02 18:47:30 +01004 * Author(s): Patrice Chotard, <patrice.chotard@foss.st.com> for STMicroelectronics.
Patrice Chotarde23b19f2018-01-18 13:39:32 +01005 */
6
7#include <common.h>
8#include <dm.h>
Simon Glass09140112020-05-10 11:40:03 -06009#include <env.h>
Simon Glass691d7192020-05-10 11:40:02 -060010#include <init.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060011#include <log.h>
Simon Glass401d1c42020-10-30 21:38:53 -060012#include <asm/global_data.h>
Patrice Chotarde23b19f2018-01-18 13:39:32 +010013
14#include <asm/io.h>
15#include <asm/arch/stm32.h>
16
17DECLARE_GLOBAL_DATA_PTR;
18
19int dram_init(void)
20{
21 int rv;
22 struct udevice *dev;
23
24 rv = uclass_get_device(UCLASS_RAM, 0, &dev);
25 if (rv) {
26 debug("DRAM init failed: %d\n", rv);
27 return rv;
28 }
29
Siva Durga Prasad Paladugu12308b12018-07-16 15:56:11 +053030 if (fdtdec_setup_mem_size_base() != 0)
Patrice Chotarde23b19f2018-01-18 13:39:32 +010031 rv = -EINVAL;
32
33 return rv;
34}
35
36int dram_init_banksize(void)
37{
38 fdtdec_setup_memory_banksize();
39
40 return 0;
41}
42
43u32 get_board_rev(void)
44{
45 return 0;
46}
47
48int board_early_init_f(void)
49{
50 return 0;
51}
52
53int board_init(void)
54{
Patrice Chotard725e09b2018-08-03 11:46:11 +020055 gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100;
Patrice Chotarde23b19f2018-01-18 13:39:32 +010056
57 return 0;
58}
59
60#ifdef CONFIG_MISC_INIT_R
61int misc_init_r(void)
62{
63 char serialno[25];
64 u32 u_id_low, u_id_mid, u_id_high;
65
66 if (!env_get("serial#")) {
67 u_id_low = readl(&STM32_U_ID->u_id_low);
68 u_id_mid = readl(&STM32_U_ID->u_id_mid);
69 u_id_high = readl(&STM32_U_ID->u_id_high);
70 sprintf(serialno, "%08x%08x%08x",
71 u_id_high, u_id_mid, u_id_low);
72 env_set("serial#", serialno);
73 }
74
75 return 0;
76}
77#endif