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Ajay Bhargav79788bb2011-09-13 22:21:58 +05301/*
2 * (C) Copyright 2011
3 * eInfochips Ltd. <www.einfochips.com>
4 * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
5 *
6 * (C) Copyright 2010
7 * Marvell Semiconductor <www.marvell.com>
8 * Contributor: Mahavir Jain <mjain@marvell.com>
9 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020010 * SPDX-License-Identifier: GPL-2.0+
Ajay Bhargav79788bb2011-09-13 22:21:58 +053011 */
12
13#ifndef __ARMADA100_FEC_H__
14#define __ARMADA100_FEC_H__
15
Ajay Bhargav79788bb2011-09-13 22:21:58 +053016#define PORT_NUM 0x0
17
18/* RX & TX descriptor command */
19#define BUF_OWNED_BY_DMA (1<<31)
20
21/* RX descriptor status */
22#define RX_EN_INT (1<<23)
23#define RX_FIRST_DESC (1<<17)
24#define RX_LAST_DESC (1<<16)
25#define RX_ERROR (1<<15)
26
27/* TX descriptor command */
28#define TX_EN_INT (1<<23)
29#define TX_GEN_CRC (1<<22)
30#define TX_ZERO_PADDING (1<<18)
31#define TX_FIRST_DESC (1<<17)
32#define TX_LAST_DESC (1<<16)
33#define TX_ERROR (1<<15)
34
35/* smi register */
36#define SMI_BUSY (1<<28) /* 0 - Write, 1 - Read */
37#define SMI_R_VALID (1<<27) /* 0 - Write, 1 - Read */
38#define SMI_OP_W (0<<26) /* Write operation */
39#define SMI_OP_R (1<<26) /* Read operation */
40
41#define HASH_ADD 0
42#define HASH_DELETE 1
43#define HASH_ADDR_TABLE_SIZE 0x4000 /* 16K (1/2K address - PCR_HS == 1) */
44#define HOP_NUMBER 12
45
46#define PHY_WAIT_ITERATIONS 1000 /* 1000 iterations * 10uS = 10mS max */
47#define PHY_WAIT_MICRO_SECONDS 10
48
49#define ETH_HW_IP_ALIGN 2 /* hw aligns IP header */
50#define ETH_EXTRA_HEADER (6+6+2+4)
51 /* dest+src addr+protocol id+crc */
52#define MAX_PKT_SIZE 1536
53
54
55/* Bit definitions of the SDMA Config Reg */
56#define SDCR_BSZ_OFF 12
57#define SDCR_BSZ8 (3<<SDCR_BSZ_OFF)
58#define SDCR_BSZ4 (2<<SDCR_BSZ_OFF)
59#define SDCR_BSZ2 (1<<SDCR_BSZ_OFF)
60#define SDCR_BSZ1 (0<<SDCR_BSZ_OFF)
61#define SDCR_BLMR (1<<6)
62#define SDCR_BLMT (1<<7)
63#define SDCR_RIFB (1<<9)
64#define SDCR_RC_OFF 2
65#define SDCR_RC_MAX_RETRANS (0xf << SDCR_RC_OFF)
66
67/* SDMA_CMD */
68#define SDMA_CMD_AT (1<<31)
69#define SDMA_CMD_TXDL (1<<24)
70#define SDMA_CMD_TXDH (1<<23)
71#define SDMA_CMD_AR (1<<15)
72#define SDMA_CMD_ERD (1<<7)
73
74
75/* Bit definitions of the Port Config Reg */
76#define PCR_HS (1<<12)
77#define PCR_EN (1<<7)
78#define PCR_PM (1<<0)
79
80/* Bit definitions of the Port Config Extend Reg */
81#define PCXR_2BSM (1<<28)
82#define PCXR_DSCP_EN (1<<21)
83#define PCXR_MFL_1518 (0<<14)
84#define PCXR_MFL_1536 (1<<14)
85#define PCXR_MFL_2048 (2<<14)
86#define PCXR_MFL_64K (3<<14)
87#define PCXR_FLP (1<<11)
88#define PCXR_PRIO_TX_OFF 3
89#define PCXR_TX_HIGH_PRI (7<<PCXR_PRIO_TX_OFF)
90
91/*
92 * * Bit definitions of the Interrupt Cause Reg
93 * * and Interrupt MASK Reg is the same
94 * */
95#define ICR_RXBUF (1<<0)
96#define ICR_TXBUF_H (1<<2)
97#define ICR_TXBUF_L (1<<3)
98#define ICR_TXEND_H (1<<6)
99#define ICR_TXEND_L (1<<7)
100#define ICR_RXERR (1<<8)
101#define ICR_TXERR_H (1<<10)
102#define ICR_TXERR_L (1<<11)
103#define ICR_TX_UDR (1<<13)
104#define ICR_MII_CH (1<<28)
105
106#define ALL_INTS (ICR_TXBUF_H | ICR_TXBUF_L | ICR_TX_UDR |\
107 ICR_TXERR_H | ICR_TXERR_L |\
108 ICR_TXEND_H | ICR_TXEND_L |\
109 ICR_RXBUF | ICR_RXERR | ICR_MII_CH)
110
111#define PHY_MASK 0x0000001f
112
113#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev)
114/* Size of a Tx/Rx descriptor used in chain list data structure */
115#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \
116 (((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN)
117
118#define RX_BUF_OFFSET 0x2
119#define RXQ 0x0 /* RX Queue 0 */
120#define TXQ 0x1 /* TX Queue 1 */
121
122struct addr_table_entry_t {
123 u32 lo;
124 u32 hi;
125};
126
127/* Bit fields of a Hash Table Entry */
128enum hash_table_entry {
129 HTEVALID = 1,
130 HTESKIP = 2,
131 HTERD = 4,
132 HTERDBIT = 2
133};
134
135struct tx_desc {
136 u32 cmd_sts; /* Command/status field */
137 u16 reserved;
138 u16 byte_cnt; /* buffer byte count */
139 u8 *buf_ptr; /* pointer to buffer for this descriptor */
140 struct tx_desc *nextdesc_p; /* Pointer to next descriptor */
141};
142
143struct rx_desc {
144 u32 cmd_sts; /* Descriptor command status */
145 u16 byte_cnt; /* Descriptor buffer byte count */
146 u16 buf_size; /* Buffer size */
147 u8 *buf_ptr; /* Descriptor buffer pointer */
148 struct rx_desc *nxtdesc_p; /* Next descriptor pointer */
149};
150
151/*
152 * Armada100 Fast Ethernet controller Registers
153 * Refer Datasheet Appendix A.22
154 */
155struct armdfec_reg {
156 u32 phyadr; /* PHY Address */
157 u32 pad1[3];
158 u32 smi; /* SMI */
159 u32 pad2[0xFB];
160 u32 pconf; /* Port configuration */
161 u32 pad3;
162 u32 pconf_ext; /* Port configuration extend */
163 u32 pad4;
164 u32 pcmd; /* Port Command */
165 u32 pad5;
166 u32 pstatus; /* Port Status */
167 u32 pad6;
168 u32 spar; /* Serial Parameters */
169 u32 pad7;
170 u32 htpr; /* Hash table pointer */
171 u32 pad8;
172 u32 fcsal; /* Flow control source address low */
173 u32 pad9;
174 u32 fcsah; /* Flow control source address high */
175 u32 pad10;
176 u32 sdma_conf; /* SDMA configuration */
177 u32 pad11;
178 u32 sdma_cmd; /* SDMA command */
179 u32 pad12;
180 u32 ic; /* Interrupt cause */
181 u32 iwc; /* Interrupt write to clear */
182 u32 im; /* Interrupt mask */
183 u32 pad13;
184 u32 *eth_idscpp[4]; /* Eth0 IP Differentiated Services Code
185 Point to Priority 0 Low */
186 u32 eth_vlan_p; /* Eth0 VLAN Priority Tag to Priority */
187 u32 pad14[3];
188 struct rx_desc *rxfdp[4]; /* Ethernet First Rx Descriptor
189 Pointer */
190 u32 pad15[4];
191 struct rx_desc *rxcdp[4]; /* Ethernet Current Rx Descriptor
192 Pointer */
193 u32 pad16[0x0C];
194 struct tx_desc *txcdp[2]; /* Ethernet Current Tx Descriptor
195 Pointer */
196};
197
198struct armdfec_device {
199 struct eth_device dev;
200 struct armdfec_reg *regs;
201 struct tx_desc *p_txdesc;
202 struct rx_desc *p_rxdesc;
203 struct rx_desc *p_rxdesc_curr;
204 u8 *p_rxbuf;
205 u8 *p_aligned_txbuf;
206 u8 *htpr; /* hash pointer */
207};
208
209#endif /* __ARMADA100_FEC_H__ */