blob: 4e18e27df44e9de9c02eff948c8d73190a2b2e04 [file] [log] [blame]
Aubrey Li26bf7de2007-03-19 01:24:52 +08001/*
2 * U-boot - traps.c Routines related to interrupts and exceptions
3 *
Aubrey Li155fd762007-04-05 18:31:18 +08004 * Copyright (c) 2005-2007 Analog Devices Inc.
Aubrey Li26bf7de2007-03-19 01:24:52 +08005 *
6 * This file is based on
7 * No original Copyright holder listed,
8 * Probabily original (C) Roman Zippel (assigned DJD, 1999)
9 *
10 * Copyright 2003 Metrowerks - for Blackfin
11 * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
12 * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
13 *
14 * (C) Copyright 2000-2004
15 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
Aubrey Li155fd762007-04-05 18:31:18 +080032 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
33 * MA 02110-1301 USA
Aubrey Li26bf7de2007-03-19 01:24:52 +080034 */
35
36#include <common.h>
37#include <linux/types.h>
38#include <asm/errno.h>
39#include <asm/irq.h>
40#include <asm/system.h>
41#include <asm/traps.h>
Aubrey Li26bf7de2007-03-19 01:24:52 +080042#include <asm/machdep.h>
43#include "cpu.h"
44#include <asm/arch/anomaly.h>
45#include <asm/cplb.h>
46#include <asm/io.h>
47
48void init_IRQ(void)
49{
50 blackfin_init_IRQ();
51 return;
52}
53
54void process_int(unsigned long vec, struct pt_regs *fp)
55{
56 printf("interrupt\n");
57 return;
58}
59
60extern unsigned int icplb_table[page_descriptor_table_size][2];
61extern unsigned int dcplb_table[page_descriptor_table_size][2];
62
63unsigned long last_cplb_fault_retx;
64
65static unsigned int cplb_sizes[4] =
66 { 1024, 4 * 1024, 1024 * 1024, 4 * 1024 * 1024 };
67
68void trap_c(struct pt_regs *regs)
69{
70 unsigned int addr;
71 unsigned long trapnr = (regs->seqstat) & SEQSTAT_EXCAUSE;
72 unsigned int i, j, size, *I0, *I1;
73 unsigned short data = 0;
74
75 switch (trapnr) {
76 /* 0x26 - Data CPLB Miss */
77 case VEC_CPLB_M:
78
79#ifdef ANOMALY_05000261
80 /*
81 * Work around an anomaly: if we see a new DCPLB fault,
82 * return without doing anything. Then,
83 * if we get the same fault again, handle it.
84 */
85 addr = last_cplb_fault_retx;
86 last_cplb_fault_retx = regs->retx;
87 printf("this time, curr = 0x%08x last = 0x%08x\n",
88 addr, last_cplb_fault_retx);
89 if (addr != last_cplb_fault_retx)
90 goto trap_c_return;
91#endif
92 data = 1;
93
94 case VEC_CPLB_I_M:
95
96 if (data) {
97 addr = *pDCPLB_FAULT_ADDR;
98 } else {
99 addr = *pICPLB_FAULT_ADDR;
100 }
101 for (i = 0; i < page_descriptor_table_size; i++) {
102 if (data) {
103 size = cplb_sizes[dcplb_table[i][1] >> 16];
104 j = dcplb_table[i][0];
105 } else {
106 size = cplb_sizes[icplb_table[i][1] >> 16];
107 j = icplb_table[i][0];
108 }
109 if ((j <= addr) && ((j + size) > addr)) {
110 debug("found %i 0x%08x\n", i, j);
111 break;
112 }
113 }
114 if (i == page_descriptor_table_size) {
115 printf("something is really wrong\n");
116 do_reset(NULL, 0, 0, NULL);
117 }
118
119 /* Turn the cache off */
120 if (data) {
121 sync();
122 asm(" .align 8; ");
123 *(unsigned int *)DMEM_CONTROL &=
124 ~(ACACHE_BCACHE | ENDCPLB | PORT_PREF0);
125 sync();
126 } else {
127 sync();
128 asm(" .align 8; ");
129 *(unsigned int *)IMEM_CONTROL &= ~(IMC | ENICPLB);
130 sync();
131 }
132
133 if (data) {
134 I0 = (unsigned int *)DCPLB_ADDR0;
135 I1 = (unsigned int *)DCPLB_DATA0;
136 } else {
137 I0 = (unsigned int *)ICPLB_ADDR0;
138 I1 = (unsigned int *)ICPLB_DATA0;
139 }
140
141 j = 0;
142 while (*I1 & CPLB_LOCK) {
143 debug("skipping %i %08p - %08x\n", j, I1, *I1);
144 *I0++;
145 *I1++;
146 j++;
147 }
148
149 debug("remove %i 0x%08x 0x%08x\n", j, *I0, *I1);
150
151 for (; j < 15; j++) {
152 debug("replace %i 0x%08x 0x%08x\n", j, I0, I0 + 1);
153 *I0++ = *(I0 + 1);
154 *I1++ = *(I1 + 1);
155 }
156
157 if (data) {
158 *I0 = dcplb_table[i][0];
159 *I1 = dcplb_table[i][1];
160 I0 = (unsigned int *)DCPLB_ADDR0;
161 I1 = (unsigned int *)DCPLB_DATA0;
162 } else {
163 *I0 = icplb_table[i][0];
164 *I1 = icplb_table[i][1];
165 I0 = (unsigned int *)ICPLB_ADDR0;
166 I1 = (unsigned int *)ICPLB_DATA0;
167 }
168
169 for (j = 0; j < 16; j++) {
170 debug("%i 0x%08x 0x%08x\n", j, *I0++, *I1++);
171 }
172
173 /* Turn the cache back on */
174 if (data) {
175 j = *(unsigned int *)DMEM_CONTROL;
176 sync();
177 asm(" .align 8; ");
178 *(unsigned int *)DMEM_CONTROL =
179 ACACHE_BCACHE | ENDCPLB | PORT_PREF0 | j;
180 sync();
181 } else {
182 sync();
183 asm(" .align 8; ");
184 *(unsigned int *)IMEM_CONTROL = IMC | ENICPLB;
185 sync();
186 }
187
188 break;
189 default:
190 /* All traps come here */
191 printf("code=[0x%x], ", (unsigned int)(regs->seqstat & 0x3f));
192 printf("stack frame=0x%x, ", (unsigned int)regs);
193 printf("bad PC=0x%04x\n", (unsigned int)regs->pc);
194 dump(regs);
195 printf("\n\n");
196
197 printf("Unhandled IRQ or exceptions!\n");
198 printf("Please reset the board \n");
199 do_reset(NULL, 0, 0, NULL);
200 }
201
202trap_c_return:
203 return;
204
205}
206
207void dump(struct pt_regs *fp)
208{
209 debug("RETE: %08lx RETN: %08lx RETX: %08lx RETS: %08lx\n",
210 fp->rete, fp->retn, fp->retx, fp->rets);
211 debug("IPEND: %04lx SYSCFG: %04lx\n", fp->ipend, fp->syscfg);
212 debug("SEQSTAT: %08lx SP: %08lx\n", (long)fp->seqstat, (long)fp);
213 debug("R0: %08lx R1: %08lx R2: %08lx R3: %08lx\n",
214 fp->r0, fp->r1, fp->r2, fp->r3);
215 debug("R4: %08lx R5: %08lx R6: %08lx R7: %08lx\n",
216 fp->r4, fp->r5, fp->r6, fp->r7);
217 debug("P0: %08lx P1: %08lx P2: %08lx P3: %08lx\n",
218 fp->p0, fp->p1, fp->p2, fp->p3);
219 debug("P4: %08lx P5: %08lx FP: %08lx\n",
220 fp->p4, fp->p5, fp->fp);
221 debug("A0.w: %08lx A0.x: %08lx A1.w: %08lx A1.x: %08lx\n",
222 fp->a0w, fp->a0x, fp->a1w, fp->a1x);
223
224 debug("LB0: %08lx LT0: %08lx LC0: %08lx\n",
225 fp->lb0, fp->lt0, fp->lc0);
226 debug("LB1: %08lx LT1: %08lx LC1: %08lx\n",
227 fp->lb1, fp->lt1, fp->lc1);
228 debug("B0: %08lx L0: %08lx M0: %08lx I0: %08lx\n",
229 fp->b0, fp->l0, fp->m0, fp->i0);
230 debug("B1: %08lx L1: %08lx M1: %08lx I1: %08lx\n",
231 fp->b1, fp->l1, fp->m1, fp->i1);
232 debug("B2: %08lx L2: %08lx M2: %08lx I2: %08lx\n",
233 fp->b2, fp->l2, fp->m2, fp->i2);
234 debug("B3: %08lx L3: %08lx M3: %08lx I3: %08lx\n",
235 fp->b3, fp->l3, fp->m3, fp->i3);
236
237 debug("DCPLB_FAULT_ADDR=%p\n", *pDCPLB_FAULT_ADDR);
238 debug("ICPLB_FAULT_ADDR=%p\n", *pICPLB_FAULT_ADDR);
239
240}