blob: a95f84e62585138f46cfffbe0a5c298ad1f87718 [file] [log] [blame]
wdenk63f34912004-01-02 15:01:32 +00001/*
2 * rtl8139.c : U-Boot driver for the RealTek RTL8139
3 *
4 * Masami Komiya (mkomiya@sonare.it)
5 *
6 * Most part is taken from rtl8139.c of etherboot
7 *
8 */
9
10/* rtl8139.c - etherboot driver for the Realtek 8139 chipset
11
12 ported from the linux driver written by Donald Becker
13 by Rainer Bawidamann (Rainer.Bawidamann@informatik.uni-ulm.de) 1999
14
15 This software may be used and distributed according to the terms
16 of the GNU Public License, incorporated herein by reference.
17
18 changes to the original driver:
19 - removed support for interrupts, switching to polling mode (yuck!)
20 - removed support for the 8129 chip (external MII)
21
22*/
23
24/*********************************************************************/
25/* Revision History */
26/*********************************************************************/
27
28/*
29 28 Dec 2002 ken_yap@users.sourceforge.net (Ken Yap)
30 Put in virt_to_bus calls to allow Etherboot relocation.
31
32 06 Apr 2001 ken_yap@users.sourceforge.net (Ken Yap)
33 Following email from Hyun-Joon Cha, added a disable routine, otherwise
34 NIC remains live and can crash the kernel later.
35
36 4 Feb 2000 espenlaub@informatik.uni-ulm.de (Klaus Espenlaub)
37 Shuffled things around, removed the leftovers from the 8129 support
38 that was in the Linux driver and added a bit more 8139 definitions.
39 Moved the 8K receive buffer to a fixed, available address outside the
40 0x98000-0x9ffff range. This is a bit of a hack, but currently the only
41 way to make room for the Etherboot features that need substantial amounts
42 of code like the ANSI console support. Currently the buffer is just below
43 0x10000, so this even conforms to the tagged boot image specification,
44 which reserves the ranges 0x00000-0x10000 and 0x98000-0xA0000. My
45 interpretation of this "reserved" is that Etherboot may do whatever it
46 likes, as long as its environment is kept intact (like the BIOS
wdenkb6e4c402004-01-02 16:05:07 +000047 variables). Hopefully fixed rtl_poll() once and for all. The symptoms
wdenk63f34912004-01-02 15:01:32 +000048 were that if Etherboot was left at the boot menu for several minutes, the
49 first eth_poll failed. Seems like I am the only person who does this.
50 First of all I fixed the debugging code and then set out for a long bug
51 hunting session. It took me about a week full time work - poking around
52 various places in the driver, reading Don Becker's and Jeff Garzik's Linux
53 driver and even the FreeBSD driver (what a piece of crap!) - and
54 eventually spotted the nasty thing: the transmit routine was acknowledging
55 each and every interrupt pending, including the RxOverrun and RxFIFIOver
wdenkb6e4c402004-01-02 16:05:07 +000056 interrupts. This confused the RTL8139 thoroughly. It destroyed the
wdenk63f34912004-01-02 15:01:32 +000057 Rx ring contents by dumping the 2K FIFO contents right where we wanted to
58 get the next packet. Oh well, what fun.
59
wdenkb6e4c402004-01-02 16:05:07 +000060 18 Jan 2000 mdc@thinguin.org (Marty Connor)
wdenk63f34912004-01-02 15:01:32 +000061 Drastically simplified error handling. Basically, if any error
62 in transmission or reception occurs, the card is reset.
63 Also, pointed all transmit descriptors to the same buffer to
wdenkb6e4c402004-01-02 16:05:07 +000064 save buffer space. This should decrease driver size and avoid
wdenk63f34912004-01-02 15:01:32 +000065 corruption because of exceeding 32K during runtime.
66
wdenkb6e4c402004-01-02 16:05:07 +000067 28 Jul 1999 (Matthias Meixner - meixner@rbg.informatik.tu-darmstadt.de)
wdenk63f34912004-01-02 15:01:32 +000068 rtl_poll was quite broken: it used the RxOK interrupt flag instead
69 of the RxBufferEmpty flag which often resulted in very bad
70 transmission performace - below 1kBytes/s.
71
72*/
73
74#include <common.h>
75#include <malloc.h>
76#include <net.h>
77#include <asm/io.h>
78#include <pci.h>
79
wdenk63f34912004-01-02 15:01:32 +000080#if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(CONFIG_NET_MULTI) && \
81 defined(CONFIG_RTL8139)
82
83#define TICKS_PER_SEC CFG_HZ
84#define TICKS_PER_MS (TICKS_PER_SEC/1000)
85
86#define RTL_TIMEOUT (1*TICKS_PER_SEC)
87
88#define ETH_FRAME_LEN 1514
89#define ETH_ALEN 6
90#define ETH_ZLEN 60
91
92/* PCI Tuning Parameters
93 Threshold is bytes transferred to chip before transmission starts. */
wdenkb6e4c402004-01-02 16:05:07 +000094#define TX_FIFO_THRESH 256 /* In bytes, rounded down to 32 byte units. */
95#define RX_FIFO_THRESH 4 /* Rx buffer level before first PCI xfer. */
96#define RX_DMA_BURST 4 /* Maximum PCI burst, '4' is 256 bytes */
97#define TX_DMA_BURST 4 /* Calculate as 16<<val. */
98#define NUM_TX_DESC 4 /* Number of Tx descriptor registers. */
wdenk63f34912004-01-02 15:01:32 +000099#define TX_BUF_SIZE ETH_FRAME_LEN /* FCS is added by the chip */
100#define RX_BUF_LEN_IDX 0 /* 0, 1, 2 is allowed - 8,16,32K rx buffer */
101#define RX_BUF_LEN (8192 << RX_BUF_LEN_IDX)
102
103#undef DEBUG_TX
104#undef DEBUG_RX
105
106#define currticks() get_timer(0)
wdenkb6e4c402004-01-02 16:05:07 +0000107#define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
108#define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
wdenk63f34912004-01-02 15:01:32 +0000109
110/* Symbolic offsets to registers. */
111enum RTL8139_registers {
112 MAC0=0, /* Ethernet hardware address. */
113 MAR0=8, /* Multicast filter. */
114 TxStatus0=0x10, /* Transmit status (four 32bit registers). */
115 TxAddr0=0x20, /* Tx descriptors (also four 32bit). */
116 RxBuf=0x30, RxEarlyCnt=0x34, RxEarlyStatus=0x36,
117 ChipCmd=0x37, RxBufPtr=0x38, RxBufAddr=0x3A,
118 IntrMask=0x3C, IntrStatus=0x3E,
119 TxConfig=0x40, RxConfig=0x44,
120 Timer=0x48, /* general-purpose counter. */
121 RxMissed=0x4C, /* 24 bits valid, write clears. */
122 Cfg9346=0x50, Config0=0x51, Config1=0x52,
123 TimerIntrReg=0x54, /* intr if gp counter reaches this value */
124 MediaStatus=0x58,
125 Config3=0x59,
126 MultiIntr=0x5C,
127 RevisionID=0x5E, /* revision of the RTL8139 chip */
128 TxSummary=0x60,
129 MII_BMCR=0x62, MII_BMSR=0x64, NWayAdvert=0x66, NWayLPAR=0x68,
130 NWayExpansion=0x6A,
131 DisconnectCnt=0x6C, FalseCarrierCnt=0x6E,
132 NWayTestReg=0x70,
133 RxCnt=0x72, /* packet received counter */
134 CSCR=0x74, /* chip status and configuration register */
135 PhyParm1=0x78,TwisterParm=0x7c,PhyParm2=0x80, /* undocumented */
136 /* from 0x84 onwards are a number of power management/wakeup frame
137 * definitions we will probably never need to know about. */
138};
139
140enum ChipCmdBits {
141 CmdReset=0x10, CmdRxEnb=0x08, CmdTxEnb=0x04, RxBufEmpty=0x01, };
142
143/* Interrupt register bits, using my own meaningful names. */
144enum IntrStatusBits {
145 PCIErr=0x8000, PCSTimeout=0x4000, CableLenChange= 0x2000,
146 RxFIFOOver=0x40, RxUnderrun=0x20, RxOverflow=0x10,
147 TxErr=0x08, TxOK=0x04, RxErr=0x02, RxOK=0x01,
148};
149enum TxStatusBits {
150 TxHostOwns=0x2000, TxUnderrun=0x4000, TxStatOK=0x8000,
151 TxOutOfWindow=0x20000000, TxAborted=0x40000000,
152 TxCarrierLost=0x80000000,
153};
154enum RxStatusBits {
155 RxMulticast=0x8000, RxPhysical=0x4000, RxBroadcast=0x2000,
156 RxBadSymbol=0x0020, RxRunt=0x0010, RxTooLong=0x0008, RxCRCErr=0x0004,
157 RxBadAlign=0x0002, RxStatusOK=0x0001,
158};
159
160enum MediaStatusBits {
161 MSRTxFlowEnable=0x80, MSRRxFlowEnable=0x40, MSRSpeed10=0x08,
162 MSRLinkFail=0x04, MSRRxPauseFlag=0x02, MSRTxPauseFlag=0x01,
163};
164
165enum MIIBMCRBits {
166 BMCRReset=0x8000, BMCRSpeed100=0x2000, BMCRNWayEnable=0x1000,
167 BMCRRestartNWay=0x0200, BMCRDuplex=0x0100,
168};
169
170enum CSCRBits {
171 CSCR_LinkOKBit=0x0400, CSCR_LinkChangeBit=0x0800,
172 CSCR_LinkStatusBits=0x0f000, CSCR_LinkDownOffCmd=0x003c0,
173 CSCR_LinkDownCmd=0x0f3c0,
174};
175
176/* Bits in RxConfig. */
177enum rx_mode_bits {
178 RxCfgWrap=0x80,
179 AcceptErr=0x20, AcceptRunt=0x10, AcceptBroadcast=0x08,
180 AcceptMulticast=0x04, AcceptMyPhys=0x02, AcceptAllPhys=0x01,
181};
182
183static int ioaddr;
184static unsigned int cur_rx,cur_tx;
185
186/* The RTL8139 can only transmit from a contiguous, aligned memory block. */
187static unsigned char tx_buffer[TX_BUF_SIZE] __attribute__((aligned(4)));
188static unsigned char rx_ring[RX_BUF_LEN+16] __attribute__((aligned(4)));
189
190static int rtl8139_probe(struct eth_device *dev, bd_t *bis);
191static int read_eeprom(int location, int addr_len);
192static void rtl_reset(struct eth_device *dev);
193static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length);
194static int rtl_poll(struct eth_device *dev);
195static void rtl_disable(struct eth_device *dev);
196
197static struct pci_device_id supported[] = {
198 {PCI_VENDOR_ID_REALTEK, PCI_DEVICE_ID_REALTEK_8139},
199 {}
200};
201
202int rtl8139_initialize(bd_t *bis)
203{
204 pci_dev_t devno;
205 int card_number = 0;
206 struct eth_device *dev;
207 u32 iobase;
208 int idx=0;
209
210 while(1){
211 /* Find RTL8139 */
212 if ((devno = pci_find_devices(supported, idx++)) < 0)
213 break;
214
215 pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
216 iobase &= ~0xf;
217
218 debug ("rtl8139: REALTEK RTL8139 @0x%x\n", iobase);
219
220 dev = (struct eth_device *)malloc(sizeof *dev);
221
222 sprintf (dev->name, "RTL8139#%d", card_number);
223
224 dev->priv = (void *) devno;
225 dev->iobase = (int)bus_to_phys(iobase);
226 dev->init = rtl8139_probe;
227 dev->halt = rtl_disable;
228 dev->send = rtl_transmit;
229 dev->recv = rtl_poll;
230
231 eth_register (dev);
232
233 card_number++;
234
235 pci_write_config_byte (devno, PCI_LATENCY_TIMER, 0x20);
236
237 udelay (10 * 1000);
238 }
239
240 return card_number;
241}
242
243static int rtl8139_probe(struct eth_device *dev, bd_t *bis)
244{
245 int i;
246 int speed10, fullduplex;
247 int addr_len;
248 unsigned short *ap = (unsigned short *)dev->enetaddr;
249
250 ioaddr = dev->iobase;
251
252 /* Bring the chip out of low-power mode. */
253 outb(0x00, ioaddr + Config1);
254
255 addr_len = read_eeprom(0,8) == 0x8129 ? 8 : 6;
256 for (i = 0; i < 3; i++)
wdenk756f5862005-04-03 15:51:42 +0000257 *ap++ = le16_to_cpu (read_eeprom(i + 7, addr_len));
wdenk63f34912004-01-02 15:01:32 +0000258
259 speed10 = inb(ioaddr + MediaStatus) & MSRSpeed10;
260 fullduplex = inw(ioaddr + MII_BMCR) & BMCRDuplex;
261
262 rtl_reset(dev);
263
264 if (inb(ioaddr + MediaStatus) & MSRLinkFail) {
265 printf("Cable not connected or other link failure\n");
266 return(0);
267 }
268
269 return 1;
270}
271
272/* Serial EEPROM section. */
273
274/* EEPROM_Ctrl bits. */
wdenkb6e4c402004-01-02 16:05:07 +0000275#define EE_SHIFT_CLK 0x04 /* EEPROM shift clock. */
276#define EE_CS 0x08 /* EEPROM chip select. */
277#define EE_DATA_WRITE 0x02 /* EEPROM chip data in. */
278#define EE_WRITE_0 0x00
279#define EE_WRITE_1 0x02
280#define EE_DATA_READ 0x01 /* EEPROM chip data out. */
wdenk63f34912004-01-02 15:01:32 +0000281#define EE_ENB (0x80 | EE_CS)
282
283/*
284 Delay between EEPROM clock transitions.
285 No extra delay is needed with 33Mhz PCI, but 66Mhz may change this.
286*/
287
wdenkb6e4c402004-01-02 16:05:07 +0000288#define eeprom_delay() inl(ee_addr)
wdenk63f34912004-01-02 15:01:32 +0000289
290/* The EEPROM commands include the alway-set leading bit. */
wdenkb6e4c402004-01-02 16:05:07 +0000291#define EE_WRITE_CMD (5)
292#define EE_READ_CMD (6)
293#define EE_ERASE_CMD (7)
wdenk63f34912004-01-02 15:01:32 +0000294
295static int read_eeprom(int location, int addr_len)
296{
297 int i;
298 unsigned int retval = 0;
299 long ee_addr = ioaddr + Cfg9346;
300 int read_cmd = location | (EE_READ_CMD << addr_len);
301
302 outb(EE_ENB & ~EE_CS, ee_addr);
303 outb(EE_ENB, ee_addr);
304 eeprom_delay();
305
306 /* Shift the read command bits out. */
307 for (i = 4 + addr_len; i >= 0; i--) {
308 int dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
309 outb(EE_ENB | dataval, ee_addr);
310 eeprom_delay();
311 outb(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
312 eeprom_delay();
313 }
314 outb(EE_ENB, ee_addr);
315 eeprom_delay();
316
317 for (i = 16; i > 0; i--) {
318 outb(EE_ENB | EE_SHIFT_CLK, ee_addr);
319 eeprom_delay();
320 retval = (retval << 1) | ((inb(ee_addr) & EE_DATA_READ) ? 1 : 0);
321 outb(EE_ENB, ee_addr);
322 eeprom_delay();
323 }
324
325 /* Terminate the EEPROM access. */
326 outb(~EE_CS, ee_addr);
327 eeprom_delay();
328 return retval;
329}
330
331static const unsigned int rtl8139_rx_config =
332 (RX_BUF_LEN_IDX << 11) |
333 (RX_FIFO_THRESH << 13) |
334 (RX_DMA_BURST << 8);
335
336static void set_rx_mode(struct eth_device *dev) {
337 unsigned int mc_filter[2];
338 int rx_mode;
339 /* !IFF_PROMISC */
340 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
341 mc_filter[1] = mc_filter[0] = 0xffffffff;
342
343 outl(rtl8139_rx_config | rx_mode, ioaddr + RxConfig);
344
345 outl(mc_filter[0], ioaddr + MAR0 + 0);
346 outl(mc_filter[1], ioaddr + MAR0 + 4);
347}
348
349static void rtl_reset(struct eth_device *dev)
350{
351 int i;
352
353 outb(CmdReset, ioaddr + ChipCmd);
354
355 cur_rx = 0;
356 cur_tx = 0;
357
358 /* Give the chip 10ms to finish the reset. */
359 for (i=0; i<100; ++i){
360 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
361 udelay (100); /* wait 100us */
362 }
363
364
365 for (i = 0; i < ETH_ALEN; i++)
366 outb(dev->enetaddr[i], ioaddr + MAC0 + i);
367
368 /* Must enable Tx/Rx before setting transfer thresholds! */
369 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
370 outl((RX_FIFO_THRESH<<13) | (RX_BUF_LEN_IDX<<11) | (RX_DMA_BURST<<8),
371 ioaddr + RxConfig); /* accept no frames yet! */
372 outl((TX_DMA_BURST<<8)|0x03000000, ioaddr + TxConfig);
373
374 /* The Linux driver changes Config1 here to use a different LED pattern
375 * for half duplex or full/autodetect duplex (for full/autodetect, the
376 * outputs are TX/RX, Link10/100, FULL, while for half duplex it uses
377 * TX/RX, Link100, Link10). This is messy, because it doesn't match
378 * the inscription on the mounting bracket. It should not be changed
379 * from the configuration EEPROM default, because the card manufacturer
380 * should have set that to match the card. */
381
382#ifdef DEBUG_RX
383 printf("rx ring address is %X\n",(unsigned long)rx_ring);
384#endif
385 outl(phys_to_bus((int)rx_ring), ioaddr + RxBuf);
386
387 /* If we add multicast support, the MAR0 register would have to be
388 * initialized to 0xffffffffffffffff (two 32 bit accesses). Etherboot
wdenkb6e4c402004-01-02 16:05:07 +0000389 * only needs broadcast (for ARP/RARP/BOOTP/DHCP) and unicast. */
wdenk63f34912004-01-02 15:01:32 +0000390
391 outb(CmdRxEnb | CmdTxEnb, ioaddr + ChipCmd);
392
393 outl(rtl8139_rx_config, ioaddr + RxConfig);
394
395 /* Start the chip's Tx and Rx process. */
396 outl(0, ioaddr + RxMissed);
397
398 /* set_rx_mode */
399 set_rx_mode(dev);
400
401 /* Disable all known interrupts by setting the interrupt mask. */
402 outw(0, ioaddr + IntrMask);
403}
404
405static int rtl_transmit(struct eth_device *dev, volatile void *packet, int length)
406{
407 unsigned int status, to;
408 unsigned long txstatus;
409 unsigned int len = length;
410
411 ioaddr = dev->iobase;
412
413 memcpy((char *)tx_buffer, (char *)packet, (int)length);
414
415#ifdef DEBUG_TX
416 printf("sending %d bytes\n", len);
417#endif
418
419 /* Note: RTL8139 doesn't auto-pad, send minimum payload (another 4
420 * bytes are sent automatically for the FCS, totalling to 64 bytes). */
421 while (len < ETH_ZLEN) {
422 tx_buffer[len++] = '\0';
423 }
424
425 outl(phys_to_bus((int)tx_buffer), ioaddr + TxAddr0 + cur_tx*4);
426 outl(((TX_FIFO_THRESH<<11) & 0x003f0000) | len,
427 ioaddr + TxStatus0 + cur_tx*4);
428
429 to = currticks() + RTL_TIMEOUT;
430
431 do {
432 status = inw(ioaddr + IntrStatus);
433 /* Only acknlowledge interrupt sources we can properly handle
434 * here - the RxOverflow/RxFIFOOver MUST be handled in the
wdenkb6e4c402004-01-02 16:05:07 +0000435 * rtl_poll() function. */
wdenk63f34912004-01-02 15:01:32 +0000436 outw(status & (TxOK | TxErr | PCIErr), ioaddr + IntrStatus);
437 if ((status & (TxOK | TxErr | PCIErr)) != 0) break;
438 } while (currticks() < to);
439
440 txstatus = inl(ioaddr + TxStatus0 + cur_tx*4);
441
442 if (status & TxOK) {
443 cur_tx = (cur_tx + 1) % NUM_TX_DESC;
444#ifdef DEBUG_TX
445 printf("tx done (%d ticks), status %hX txstatus %X\n",
446 to-currticks(), status, txstatus);
447#endif
448 return length;
449 } else {
450#ifdef DEBUG_TX
451 printf("tx timeout/error (%d ticks), status %hX txstatus %X\n",
452 currticks()-to, status, txstatus);
453#endif
454 rtl_reset(dev);
455
456 return 0;
457 }
458}
459
460static int rtl_poll(struct eth_device *dev)
461{
462 unsigned int status;
463 unsigned int ring_offs;
464 unsigned int rx_size, rx_status;
465 int length=0;
466
467 ioaddr = dev->iobase;
468
469 if (inb(ioaddr + ChipCmd) & RxBufEmpty) {
470 return 0;
471 }
472
473 status = inw(ioaddr + IntrStatus);
474 /* See below for the rest of the interrupt acknowledges. */
475 outw(status & ~(RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
476
477#ifdef DEBUG_RX
478 printf("rtl_poll: int %hX ", status);
479#endif
480
481 ring_offs = cur_rx % RX_BUF_LEN;
482 rx_status = *(unsigned int*)KSEG1ADDR((rx_ring + ring_offs));
483 rx_size = rx_status >> 16;
484 rx_status &= 0xffff;
485
486 if ((rx_status & (RxBadSymbol|RxRunt|RxTooLong|RxCRCErr|RxBadAlign)) ||
487 (rx_size < ETH_ZLEN) || (rx_size > ETH_FRAME_LEN + 4)) {
488 printf("rx error %hX\n", rx_status);
wdenkb6e4c402004-01-02 16:05:07 +0000489 rtl_reset(dev); /* this clears all interrupts still pending */
wdenk63f34912004-01-02 15:01:32 +0000490 return 0;
491 }
492
493 /* Received a good packet */
494 length = rx_size - 4; /* no one cares about the FCS */
495 if (ring_offs+4+rx_size-4 > RX_BUF_LEN) {
496 int semi_count = RX_BUF_LEN - ring_offs - 4;
497 unsigned char rxdata[RX_BUF_LEN];
498
499 memcpy(rxdata, rx_ring + ring_offs + 4, semi_count);
500 memcpy(&(rxdata[semi_count]), rx_ring, rx_size-4-semi_count);
501
502 NetReceive(rxdata, length);
503#ifdef DEBUG_RX
504 printf("rx packet %d+%d bytes", semi_count,rx_size-4-semi_count);
505#endif
506 } else {
507 NetReceive(rx_ring + ring_offs + 4, length);
508#ifdef DEBUG_RX
509 printf("rx packet %d bytes", rx_size-4);
510#endif
511 }
512
513 cur_rx = (cur_rx + rx_size + 4 + 3) & ~3;
514 outw(cur_rx - 16, ioaddr + RxBufPtr);
515 /* See RTL8139 Programming Guide V0.1 for the official handling of
516 * Rx overflow situations. The document itself contains basically no
517 * usable information, except for a few exception handling rules. */
518 outw(status & (RxFIFOOver | RxOverflow | RxOK), ioaddr + IntrStatus);
519 return length;
520}
521
522static void rtl_disable(struct eth_device *dev)
523{
524 int i;
525
wdenkb6e4c402004-01-02 16:05:07 +0000526 ioaddr = dev->iobase;
527
wdenk63f34912004-01-02 15:01:32 +0000528 /* reset the chip */
529 outb(CmdReset, ioaddr + ChipCmd);
530
531 /* Give the chip 10ms to finish the reset. */
532 for (i=0; i<100; ++i){
533 if ((inb(ioaddr + ChipCmd) & CmdReset) == 0) break;
534 udelay (100); /* wait 100us */
535 }
536}
537#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_RTL8139 */