| Heiko Schocher | 7bdfe85 | 2020-02-03 07:43:57 +0100 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| Holger Brunck | 5d57dfa | 2020-10-08 12:27:22 +0200 | [diff] [blame] | 3 | * Hitachi Power Grids km836x common ports Device Tree Source |
| Heiko Schocher | 7bdfe85 | 2020-02-03 07:43:57 +0100 | [diff] [blame] | 4 | * |
| 5 | * Copyright (C) 2020 Heiko Schocher <hs@denx.de> |
| 6 | * |
| 7 | */ |
| 8 | |
| 9 | /dts-v1/; |
| 10 | |
| 11 | / { |
| 12 | #address-cells = <1>; |
| 13 | #size-cells = <1>; |
| 14 | |
| 15 | cpus { |
| 16 | #address-cells = <1>; |
| 17 | #size-cells = <0>; |
| 18 | |
| 19 | PowerPC,8360@0 { |
| 20 | device_type = "cpu"; |
| 21 | reg = <0x0>; |
| 22 | d-cache-line-size = <32>; /* 32 bytes */ |
| 23 | i-cache-line-size = <32>; /* 32 bytes */ |
| 24 | d-cache-size = <32768>; /* L1, 32K */ |
| 25 | i-cache-size = <32768>; /* L1, 32K */ |
| 26 | timebase-frequency = <0>; /* Filled in by U-Boot */ |
| 27 | bus-frequency = <0>; /* Filled in by U-Boot */ |
| 28 | clock-frequency = <0>; /* Filled in by U-Boot */ |
| 29 | }; |
| 30 | }; |
| 31 | |
| 32 | memory { |
| 33 | device_type = "memory"; |
| 34 | reg = <0 0>; /* Filled in by U-Boot */ |
| 35 | }; |
| 36 | |
| 37 | soc: soc8360@e0000000 { |
| 38 | #address-cells = <1>; |
| 39 | #size-cells = <1>; |
| 40 | device_type = "soc"; |
| 41 | compatible = "fsl,mpc8360-immr", "simple-bus"; |
| 42 | ranges = <0x0 0xe0000000 0x00200000>; |
| 43 | reg = <0xe0000000 0x00000200>; |
| 44 | bus-frequency = <0>;/* Filled in by U-Boot */ |
| 45 | |
| 46 | /* power management control module*/ |
| 47 | pmc: power@b00 { |
| 48 | compatible = "fsl,mpc8360-pmc", "fsl,mpc8349-pmc"; |
| 49 | reg = <0xb00 0x100 0xa00 0x100>; |
| 50 | interrupts = <80 0x8>; |
| 51 | interrupt-parent = <&ipic>; |
| 52 | }; |
| 53 | |
| 54 | i2c0: i2c@3000 { |
| 55 | #address-cells = <1>; |
| 56 | #size-cells = <0>; |
| 57 | cell-index = <0>; |
| 58 | compatible = "fsl,mpc8313-i2c","fsl-i2c"; |
| 59 | reg = <0x3000 0x100>; |
| 60 | interrupts = <14 0x8>; |
| 61 | interrupt-parent = <&ipic>; |
| 62 | clock-frequency = <100000>; |
| 63 | }; |
| 64 | |
| 65 | serial0: serial@4500 { |
| 66 | cell-index = <0>; |
| 67 | device_type = "serial"; |
| 68 | compatible = "fsl,ns16550", "ns16550"; |
| 69 | reg = <0x4500 0x100>; |
| 70 | clock-frequency = <264000000>; |
| 71 | interrupts = <9 0x8>; |
| 72 | interrupt-parent = <&ipic>; |
| 73 | status = "disabled"; |
| 74 | }; |
| 75 | |
| 76 | serial1: serial@4600 { |
| 77 | cell-index = <1>; |
| 78 | device_type = "serial"; |
| 79 | compatible = "fsl,ns16550", "ns16550"; |
| 80 | reg = <0x4600 0x100>; |
| 81 | clock-frequency = <133333333>; |
| 82 | interrupts = <10 0x8>; |
| 83 | interrupt-parent = <&ipic>; |
| 84 | status = "disabled"; |
| 85 | }; |
| 86 | |
| 87 | ipic: pic@700 { |
| 88 | #address-cells = <0>; |
| 89 | #interrupt-cells = <2>; |
| 90 | compatible = "fsl,pq2pro-pic", "fsl,ipic"; |
| 91 | interrupt-controller; |
| 92 | reg = <0x700 0x100>; |
| 93 | }; |
| 94 | |
| 95 | par_io: par_io@1400 { |
| 96 | #address-cells = <1>; |
| 97 | #size-cells = <1>; |
| 98 | reg = <0x1400 0x100>; |
| 99 | ranges; |
| 100 | compatible = "fsl,mpc8360-par_io"; |
| 101 | device_type = "par_io"; |
| 102 | num-ports = <7>; |
| 103 | |
| 104 | qe_pio_c: gpio-controller@30 { |
| 105 | #gpio-cells = <2>; |
| 106 | compatible = "fsl,mpc8360-qe-pario-bank", |
| 107 | "fsl,mpc8323-qe-pario-bank"; |
| 108 | reg = <0x1430 0x18>; |
| 109 | gpio-controller; |
| 110 | }; |
| 111 | }; |
| 112 | |
| 113 | qe: qe@100000 { |
| 114 | #address-cells = <1>; |
| 115 | #size-cells = <1>; |
| 116 | compatible = "fsl,qe"; |
| 117 | ranges = <0x0 0x100000 0x100000>; |
| 118 | reg = <0x100000 0x480>; |
| 119 | clock-frequency = <0>; /* Filled in by U-Boot */ |
| 120 | brg-frequency = <0>; /* Filled in by U-Boot */ |
| 121 | bus-frequency = <0>; /* Filled in by U-Boot */ |
| 122 | |
| 123 | muram@10000 { |
| 124 | #address-cells = <1>; |
| 125 | #size-cells = <1>; |
| 126 | compatible = "fsl,qe-muram", "fsl,cpm-muram"; |
| 127 | ranges = <0x0 0x00010000 0x0000c000>; |
| 128 | |
| 129 | data-only@0 { |
| 130 | compatible = "fsl,qe-muram-data", |
| 131 | "fsl,cpm-muram-data"; |
| 132 | reg = <0x0 0xc000>; |
| 133 | }; |
| 134 | }; |
| 135 | |
| 136 | qeic: interrupt-controller@80 { |
| 137 | interrupt-controller; |
| 138 | compatible = "fsl,qe-ic"; |
| 139 | #address-cells = <0>; |
| 140 | #interrupt-cells = <1>; |
| 141 | reg = <0x80 0x80>; |
| 142 | big-endian; |
| 143 | interrupts = < |
| 144 | 32 0x8 /* ucc1 */ |
| 145 | 33 0x8 /* ucc2 */ |
| 146 | 34 0x8 /* ucc3 */ |
| 147 | 35 0x8 /* ucc4 */ |
| 148 | 40 0x8 /* ucc1 */ |
| 149 | >; |
| 150 | interrupt-parent = <&ipic>; |
| 151 | }; |
| 152 | |
| 153 | spi0: spi@4c0 { |
| 154 | cell-index = <0>; |
| 155 | compatible = "fsl,spi"; |
| 156 | reg = <0x4c0 0x40>; |
| 157 | interrupts = <2>; |
| 158 | interrupt-parent = <&qeic>; |
| 159 | mode = "qe"; |
| 160 | #address-cells = <1>; |
| 161 | #size-cells = <0>; |
| 162 | pio-handle = <&pio_spi>; |
| 163 | }; |
| 164 | |
| 165 | bootcount@0x1bff8 { |
| 166 | device_type = "bootcount"; |
| 167 | compatible = "u-boot,bootcount"; |
| 168 | reg = <0x1bff8 0x08>; |
| 169 | }; |
| 170 | }; |
| 171 | }; |
| 172 | |
| 173 | localbus: localbus@e0005000 { |
| 174 | #address-cells = <2>; |
| 175 | #size-cells = <1>; |
| 176 | compatible = "fsl,mpc8360-localbus", "fsl,pq2pro-localbus", |
| 177 | "simple-bus"; |
| 178 | reg = <0xe0005000 0xd8>; |
| 179 | }; |
| 180 | }; |
| 181 | |
| 182 | #include "km836x-uboot.dtsi" |