blob: 84d32360baa53216d80b122bd1f108eada8ef512 [file] [log] [blame]
Hou Zhiqiangcaa75692019-08-20 09:35:29 +00001// SPDX-License-Identifier: GPL-2.0+ OR X11
2/*
3 * P2020RDB-PC Device Tree Source
4 *
5 * Copyright 2013 - 2015 Freescale Semiconductor Inc.
6 * Copyright 2019 NXP
7 */
8
9/include/ "p2020.dtsi"
10
11/ {
12 model = "fsl,P2020RDB-PC";
13 compatible = "fsl,P2020RDB-PC";
14 #address-cells = <2>;
15 #size-cells = <2>;
16 interrupt-parent = <&mpic>;
17
Pali Rohár7d1d31d2022-04-05 11:15:21 +020018 lbc: localbus@ffe05000 {
19 reg = <0 0xffe05000 0 0x1000>;
20 };
21
Hou Zhiqiangcaa75692019-08-20 09:35:29 +000022 soc: soc@ffe00000 {
23 ranges = <0x0 0x0 0xffe00000 0x100000>;
24 };
Hou Zhiqiang68751492019-08-27 11:04:15 +000025
26 pci2: pcie@ffe08000 {
27 reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
28 status = "disabled";
29 };
30
31 pci1: pcie@ffe09000 {
32 reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
33 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
34 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
35 };
36
37 pci0: pcie@ffe0a000 {
38 reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
39 ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
40 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
41 };
Xiaowei Bao76b6db62020-06-04 23:16:38 +080042
43 aliases {
44 spi0 = &espi0;
45 };
Hou Zhiqiangcaa75692019-08-20 09:35:29 +000046};
47
Hou Zhiqiang613e49b2020-09-21 15:16:23 +053048/include/ "p2020rdb-pc.dtsi"
Hou Zhiqiangcaa75692019-08-20 09:35:29 +000049/include/ "p2020-post.dtsi"
Xiaowei Bao76b6db62020-06-04 23:16:38 +080050
51&espi0 {
Xiaowei Bao76b6db62020-06-04 23:16:38 +080052 flash@0 {
53 compatible = "jedec,spi-nor";
54 #address-cells = <1>;
55 #size-cells = <1>;
56 reg = <0>;
57 spi-max-frequency = <10000000>; /* input clock */
58 };
59};