blob: f0702cab14316d37f2838180e7d97fc3d910e43d [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Kumar Gala47d41cc2009-02-05 20:40:57 -06002/*
Poonam Aggrwalb8cdd012011-01-13 21:39:27 +05303 * Copyright 2009-2011 Freescale Semiconductor, Inc.
Kumar Gala47d41cc2009-02-05 20:40:57 -06004 */
5
6#ifndef _ASM_CONFIG_H_
7#define _ASM_CONFIG_H_
8
Kumar Gala243be8e2011-01-19 03:05:26 -06009#ifdef CONFIG_MPC85xx
10#include <asm/config_mpc85xx.h>
11#endif
12
York Sun7ac3cc22012-08-17 09:00:54 +000013#ifndef HWCONFIG_BUFFER_SIZE
14 #define HWCONFIG_BUFFER_SIZE 256
15#endif
16
Tom Rini1d457db2022-12-04 10:04:50 -050017#ifndef CFG_MAX_MEM_MAPPED
Heiko Schocher98f705c2017-06-27 16:49:14 +020018#if defined(CONFIG_E500) || \
York Sund29d17d2011-08-26 11:32:44 -070019 defined(CONFIG_MPC86xx) || \
20 defined(CONFIG_E300)
Tom Rini1d457db2022-12-04 10:04:50 -050021#define CFG_MAX_MEM_MAPPED ((phys_size_t)2 << 30)
Kumar Gala87c90632009-02-05 20:40:58 -060022#else
Tom Rini1d457db2022-12-04 10:04:50 -050023#define CFG_MAX_MEM_MAPPED (256 << 20)
Kumar Gala87c90632009-02-05 20:40:58 -060024#endif
25#endif
26
Peter Tyser5ccd29c2009-10-23 15:55:47 -050027/*
28 * Provide a default boot page translation virtual address that lines up with
29 * Freescale's default e500 reset page.
30 */
31#if (defined(CONFIG_E500) && defined(CONFIG_MP))
Tom Rini0b5870c2022-03-11 09:12:03 -050032#define BPTR_VIRT_ADDR 0xfffff000
Peter Tyser5ccd29c2009-10-23 15:55:47 -050033#endif
34
Andy Fleming063c1262011-04-08 02:10:54 -050035/* The TSEC driver uses the PHYLIB infrastructure */
Zhao Qiang990d06b2018-02-07 10:01:56 +080036#if defined(CONFIG_TSEC_ENET) && defined(CONFIG_PHYLIB)
Andy Fleming063c1262011-04-08 02:10:54 -050037#include <config_phylib_all_drivers.h>
38#endif /* TSEC_ENET */
Andy Fleming063c1262011-04-08 02:10:54 -050039
Kumar Galac916d7c2011-04-13 08:37:44 -050040/* The FMAN driver uses the PHYLIB infrastructure */
Kumar Galac916d7c2011-04-13 08:37:44 -050041
Mario Six07d538d2018-08-06 10:23:36 +020042#if defined(CONFIG_DM_SERIAL) && !defined(CONFIG_CLK_MPC83XX)
Thomas Chouf27445c2015-11-19 21:48:07 +080043/*
44 * TODO: Convert this to a clock driver exists that can give us the UART
45 * clock here.
46 */
Tom Rini91092132022-11-16 13:10:28 -050047#define CFG_SYS_NS16550_CLK get_serial_clock()
Thomas Chouf27445c2015-11-19 21:48:07 +080048#endif
49
Peter Tyser017f11f2009-06-30 17:15:40 -050050#endif /* _ASM_CONFIG_H_ */