blob: a71537812794697d245b2b5402190f26ac606ac2 [file] [log] [blame]
Sam Shihac57e2b2020-01-10 16:30:26 +08001// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2019 MediaTek Inc.
4 * Author: Sam Shih <sam.shih@mediatek.com>
5 */
6
7#include <common.h>
8#include <fdtdec.h>
9#include <asm/armv8/mmu.h>
Simon Glass90526e92020-05-10 11:39:56 -060010#include <asm/cache.h>
Sam Shihac57e2b2020-01-10 16:30:26 +080011
12int print_cpuinfo(void)
13{
14 printf("CPU: MediaTek MT7622\n");
15 return 0;
16}
17
18int dram_init(void)
19{
20 int ret;
21
22 ret = fdtdec_setup_memory_banksize();
23 if (ret)
24 return ret;
25 return fdtdec_setup_mem_size_base();
26
27}
28
29void reset_cpu(ulong addr)
30{
31 psci_system_reset();
32}
33
34static struct mm_region mt7622_mem_map[] = {
35 {
36 /* DDR */
37 .virt = 0x40000000UL,
38 .phys = 0x40000000UL,
39 .size = 0x40000000UL,
40 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
41 }, {
42 .virt = 0x00000000UL,
43 .phys = 0x00000000UL,
44 .size = 0x40000000UL,
45 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
46 PTE_BLOCK_NON_SHARE |
47 PTE_BLOCK_PXN | PTE_BLOCK_UXN
48 }, {
49 0,
50 }
51};
52struct mm_region *mem_map = mt7622_mem_map;