blob: 32168d35768a1a6375c2497276b5ed7294239c81 [file] [log] [blame]
Dirk Eibach60083262017-02-22 16:07:23 +01001/*
2 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
3 * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <dm.h>
10#include <miiphy.h>
11#include <tpm.h>
12#include <asm/io.h>
13#include <asm/arch/cpu.h>
14#include <asm-generic/gpio.h>
15
16#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
17#include "../arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.h"
18
19#include "keyprogram.h"
20#include "dt_helpers.h"
21#include "hydra.h"
22#include "ihs_phys.h"
23
24DECLARE_GLOBAL_DATA_PTR;
25
26#define ETH_PHY_CTRL_REG 0
27#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
28#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
29
30#define DB_GP_88F68XX_GPP_OUT_ENA_LOW 0x7fffffff
31#define DB_GP_88F68XX_GPP_OUT_ENA_MID 0xffffefff
32
33#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
34#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x00001000
35#define DB_GP_88F68XX_GPP_POL_LOW 0x0
36#define DB_GP_88F68XX_GPP_POL_MID 0x0
37
38/*
39 * Define the DDR layout / topology here in the board file. This will
40 * be used by the DDR3 init code in the SPL U-Boot version to configure
41 * the DDR3 controller.
42 */
43static struct hws_topology_map ddr_topology_map = {
44 0x1, /* active interfaces */
45 /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
46 { { { {0x1, 0, 0, 0},
47 {0x1, 0, 0, 0},
48 {0x1, 0, 0, 0},
49 {0x1, 0, 0, 0},
50 {0x1, 0, 0, 0} },
51 SPEED_BIN_DDR_1600K, /* speed_bin */
52 BUS_WIDTH_16, /* memory_width */
53 MEM_4G, /* mem_size */
54 DDR_FREQ_533, /* frequency */
55 0, 0, /* cas_l cas_wl */
Marek BehĂșn90bcc3d2017-06-09 19:28:40 +020056 HWS_TEMP_LOW, /* temperature */
57 HWS_TIM_DEFAULT} }, /* timing */
Dirk Eibach60083262017-02-22 16:07:23 +010058 5, /* Num Of Bus Per Interface*/
59 BUS_MASK_32BIT /* Busses mask */
60};
61
62static struct serdes_map serdes_topology_map[] = {
63 {SGMII0, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
64 {USB3_HOST0, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0},
65 /* SATA tx polarity is inverted */
66 {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 1},
67 {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0},
68 {DEFAULT_SERDES, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0},
69 {PEX2, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}
70};
71
72int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
73{
74 *serdes_map_array = serdes_topology_map;
75 *count = ARRAY_SIZE(serdes_topology_map);
76 return 0;
77}
78
79void board_pex_config(void)
80{
81#ifdef CONFIG_SPL_BUILD
82 uint k;
83 struct gpio_desc gpio = {};
84
85 if (!request_gpio_by_name(&gpio, "pca9698@22", 31, "fpga-program-gpio")) {
86 /* prepare FPGA reconfiguration */
87 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
88 dm_gpio_set_value(&gpio, 0);
89
90 /* give lunatic PCIe clock some time to stabilize */
91 mdelay(500);
92
93 /* start FPGA reconfiguration */
94 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_IN);
95 }
96
97 /* wait for FPGA done */
98 if (!request_gpio_by_name(&gpio, "pca9698@22", 19, "fpga-done-gpio")) {
99 for (k = 0; k < 20; ++k) {
100 if (dm_gpio_get_value(&gpio)) {
101 printf("FPGA done after %u rounds\n", k);
102 break;
103 }
104 mdelay(100);
105 }
106 }
107
108 /* disable FPGA reset */
109 if (!request_gpio_by_name(&gpio, "gpio@18100", 6, "cpu-to-fpga-reset")) {
110 dm_gpio_set_dir_flags(&gpio, GPIOD_IS_OUT);
111 dm_gpio_set_value(&gpio, 1);
112 }
113
114 /* wait for FPGA ready */
115 if (!request_gpio_by_name(&gpio, "pca9698@22", 27, "fpga-ready-gpio")) {
116 for (k = 0; k < 2; ++k) {
117 if (!dm_gpio_get_value(&gpio))
118 break;
119 mdelay(100);
120 }
121 }
122#endif
123}
124
125struct hws_topology_map *ddr3_get_topology_map(void)
126{
127 return &ddr_topology_map;
128}
129
130int board_early_init_f(void)
131{
132#ifdef CONFIG_SPL_BUILD
133 /* Configure MPP */
134 writel(0x00111111, MVEBU_MPP_BASE + 0x00);
135 writel(0x40040000, MVEBU_MPP_BASE + 0x04);
136 writel(0x00466444, MVEBU_MPP_BASE + 0x08);
137 writel(0x00043300, MVEBU_MPP_BASE + 0x0c);
138 writel(0x44400000, MVEBU_MPP_BASE + 0x10);
139 writel(0x20000334, MVEBU_MPP_BASE + 0x14);
140 writel(0x40000000, MVEBU_MPP_BASE + 0x18);
141 writel(0x00004444, MVEBU_MPP_BASE + 0x1c);
142
143 /* Set GPP Out value */
144 writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
145 writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
146
147 /* Set GPP Polarity */
148 writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
149 writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
150
151 /* Set GPP Out Enable */
152 writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
153 writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
154#endif
155
156 return 0;
157}
158
159int board_init(void)
160{
161 /* Address of boot parameters */
162 gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
163
164 return 0;
165}
166
167#ifndef CONFIG_SPL_BUILD
168void init_host_phys(struct mii_dev *bus)
169{
170 uint k;
171
172 for (k = 0; k < 2; ++k) {
173 struct phy_device *phydev;
174
175 phydev = phy_find_by_mask(bus, 1 << k,
176 PHY_INTERFACE_MODE_SGMII);
177
178 if (phydev)
179 phy_config(phydev);
180 }
181}
182
183int ccdc_eth_init(void)
184{
185 uint k;
186 uint octo_phy_mask = 0;
187 int ret;
188 struct mii_dev *bus;
189
190 /* Init SoC's phys */
191 bus = miiphy_get_dev_by_name("ethernet@34000");
192
193 if (bus)
194 init_host_phys(bus);
195
196 bus = miiphy_get_dev_by_name("ethernet@70000");
197
198 if (bus)
199 init_host_phys(bus);
200
201 /* Init octo phys */
202 octo_phy_mask = calculate_octo_phy_mask();
203
204 printf("IHS PHYS: %08x", octo_phy_mask);
205
206 ret = init_octo_phys(octo_phy_mask);
207
208 if (ret)
209 return ret;
210
211 printf("\n");
212
213 if (!get_fpga()) {
214 puts("fpga was NULL\n");
215 return 1;
216 }
217
218 /* reset all FPGA-QSGMII instances */
219 for (k = 0; k < 80; ++k)
220 writel(1 << 31, get_fpga()->qsgmii_port_state[k]);
221
222 udelay(100);
223
224 for (k = 0; k < 80; ++k)
225 writel(0, get_fpga()->qsgmii_port_state[k]);
226 return 0;
227}
228
229#endif
230
231int board_late_init(void)
232{
233#ifndef CONFIG_SPL_BUILD
234 hydra_initialize();
235#endif
236 return 0;
237}
238
239int board_fix_fdt(void *rw_fdt_blob)
240{
241 struct udevice *bus = NULL;
242 uint k;
243 char name[64];
244 int err;
245
246 err = uclass_get_device_by_name(UCLASS_I2C, "i2c@11000", &bus);
247
248 if (err) {
249 printf("Could not get I2C bus.\n");
250 return err;
251 }
252
253 for (k = 0x21; k <= 0x26; k++) {
254 snprintf(name, 64,
255 "/soc/internal-regs/i2c@11000/pca9698@%02x", k);
256
257 if (!dm_i2c_simple_probe(bus, k))
258 fdt_disable_by_ofname(rw_fdt_blob, name);
259 }
260
261 return 0;
262}
263
264int last_stage_init(void)
265{
266#ifndef CONFIG_SPL_BUILD
267 ccdc_eth_init();
268#endif
269 if (tpm_init() || tpm_startup(TPM_ST_CLEAR) ||
270 tpm_continue_self_test()) {
271 return 1;
272 }
273
274 mdelay(37);
275
276 flush_keys();
277 load_and_run_keyprog();
278
279 return 0;
280}