| Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> |
| 4 | * Andreas Heppel <aheppel@sysgo.de> |
| wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _MPC106_PCI_H |
| 8 | #define _MPC106_PCI_H |
| 9 | |
| 10 | /* |
| 11 | * Defines for the MPC106 PCI Config address and data registers followed by |
| 12 | * defines for the standard PCI device configuration header. |
| 13 | */ |
| Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 14 | #define PCIDEVID_MPC106 0x0 |
| wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 15 | |
| 16 | /* |
| 17 | * MPC106 Registers |
| 18 | */ |
| 19 | #define MPC106_REG 0x80000000 |
| 20 | |
| Jean-Christophe PLAGNIOL-VILLARD | 6d0f6bc | 2008-10-16 15:01:15 +0200 | [diff] [blame] | 21 | #ifdef CONFIG_SYS_ADDRESS_MAP_A |
| Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 22 | #define MPC106_REG_ADDR 0x80000cf8 |
| wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 23 | #define MPC106_REG_DATA 0x80000cfc |
| 24 | #define MPC106_ISA_IO_PHYS 0x80000000 |
| 25 | #define MPC106_ISA_IO_BUS 0x00000000 |
| 26 | #define MPC106_ISA_IO_SIZE 0x00800000 |
| 27 | #define MPC106_PCI_IO_PHYS 0x81000000 |
| 28 | #define MPC106_PCI_IO_BUS 0x01000000 |
| 29 | #define MPC106_PCI_IO_SIZE 0x3e800000 |
| 30 | #define MPC106_PCI_MEM_PHYS 0xc0000000 |
| 31 | #define MPC106_PCI_MEM_BUS 0x00000000 |
| 32 | #define MPC106_PCI_MEM_SIZE 0x3f000000 |
| 33 | #define MPC106_PCI_MEMORY_PHYS 0x00000000 |
| 34 | #define MPC106_PCI_MEMORY_BUS 0x80000000 |
| 35 | #define MPC106_PCI_MEMORY_SIZE 0x80000000 |
| 36 | #else |
| Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 37 | #define MPC106_REG_ADDR 0xfec00cf8 |
| wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 38 | #define MPC106_REG_DATA 0xfee00cfc |
| 39 | #define MPC106_ISA_MEM_PHYS 0xfd000000 |
| 40 | #define MPC106_ISA_MEM_BUS 0x00000000 |
| 41 | #define MPC106_ISA_MEM_SIZE 0x01000000 |
| 42 | #define MPC106_ISA_IO_PHYS 0xfe000000 |
| 43 | #define MPC106_ISA_IO_BUS 0x00000000 |
| 44 | #define MPC106_ISA_IO_SIZE 0x00800000 |
| 45 | #define MPC106_PCI_IO_PHYS 0xfe800000 |
| 46 | #define MPC106_PCI_IO_BUS 0x00800000 |
| 47 | #define MPC106_PCI_IO_SIZE 0x00400000 |
| 48 | #define MPC106_PCI_MEM_PHYS 0x80000000 |
| 49 | #define MPC106_PCI_MEM_BUS 0x80000000 |
| 50 | #define MPC106_PCI_MEM_SIZE 0x7d000000 |
| 51 | #define MPC106_PCI_MEMORY_PHYS 0x00000000 |
| 52 | #define MPC106_PCI_MEMORY_BUS 0x00000000 |
| 53 | #define MPC106_PCI_MEMORY_SIZE 0x40000000 |
| 54 | #endif |
| 55 | |
| 56 | #define CMD_SERR 0x0100 |
| 57 | #define PCI_CMD_MASTER 0x0004 |
| 58 | #define PCI_CMD_MEMEN 0x0002 |
| 59 | #define PCI_CMD_IOEN 0x0001 |
| 60 | |
| 61 | #define PCI_STAT_NO_RSV_BITS 0xffff |
| 62 | |
| Wolfgang Denk | 53677ef | 2008-05-20 16:00:29 +0200 | [diff] [blame] | 63 | #define PCI_BUSNUM 0x40 |
| 64 | #define PCI_SUBBUSNUM 0x41 |
| 65 | #define PCI_DISCOUNT 0x42 |
| wdenk | 1df49e2 | 2002-09-17 21:37:55 +0000 | [diff] [blame] | 66 | |
| 67 | #define PCI_PICR1 0xA8 |
| 68 | #define PICR1_CF_CBA(value) ((value & 0xff) << 24) |
| 69 | #define PICR1_CF_BREAD_WS(value) ((value & 0x3) << 22) |
| 70 | #define PICR1_PROC_TYPE_603 0x40000 |
| 71 | #define PICR1_PROC_TYPE_604 0x60000 |
| 72 | #define PICR1_MCP_EN 0x800 |
| 73 | #define PICR1_CF_DPARK 0x200 |
| 74 | #define PICR1_CF_LOOP_SNOOP 0x10 |
| 75 | #define PICR1_CF_L2_COPY_BACK 0x2 |
| 76 | #define PICR1_CF_L2_CACHE_MASK 0x3 |
| 77 | #define PICR1_CF_APARK 0x8 |
| 78 | #define PICR1_ADDRESS_MAP 0x10000 |
| 79 | #define PICR1_XIO_MODE 0x80000 |
| 80 | #define PICR1_CF_CACHE_1G 0x200000 |
| 81 | |
| 82 | #define PCI_PICR2 0xAC |
| 83 | #define PICR2_CF_SNOOP_WS(value) ((value & 0x3) << 18) |
| 84 | #define PICR2_CF_FLUSH_L2 0x10000000 |
| 85 | #define PICR2_CF_L2_HIT_DELAY(value) ((value & 0x3) << 9) |
| 86 | #define PICR2_CF_APHASE_WS(value) ((value & 0x3) << 2) |
| 87 | #define PICR2_CF_INV_MODE 0x00001000 |
| 88 | #define PICR2_CF_MOD_HIGH 0x00020000 |
| 89 | #define PICR2_CF_HIT_HIGH 0x00010000 |
| 90 | #define PICR2_L2_SIZE_256K 0x00000000 |
| 91 | #define PICR2_L2_SIZE_512K 0x00000010 |
| 92 | #define PICR2_L2_SIZE_1MB 0x00000020 |
| 93 | #define PICR2_L2_EN 0x40000000 |
| 94 | #define PICR2_L2_UPDATE_EN 0x80000000 |
| 95 | #define PICR2_CF_ADDR_ONLY_DISABLE 0x00004000 |
| 96 | #define PICR2_CF_FAST_CASTOUT 0x00000080 |
| 97 | #define PICR2_CF_WDATA 0x00000001 |
| 98 | #define PICR2_CF_DATA_RAM_PBURST 0x00400000 |
| 99 | |
| 100 | /* |
| 101 | * Memory controller |
| 102 | */ |
| 103 | #define MPC106_MCCR1 0xF0 |
| 104 | #define MCCR1_TYPE_EDO 0x00020000 |
| 105 | #define MCCR1_BK0_9BITS 0x0 |
| 106 | #define MCCR1_BK0_10BITS 0x1 |
| 107 | #define MCCR1_BK0_11BITS 0x2 |
| 108 | #define MCCR1_BK0_12BITS 0x3 |
| 109 | #define MCCR1_BK1_9BITS 0x0 |
| 110 | #define MCCR1_BK1_10BITS 0x4 |
| 111 | #define MCCR1_BK1_11BITS 0x8 |
| 112 | #define MCCR1_BK1_12BITS 0xC |
| 113 | #define MCCR1_BK2_9BITS 0x00 |
| 114 | #define MCCR1_BK2_10BITS 0x10 |
| 115 | #define MCCR1_BK2_11BITS 0x20 |
| 116 | #define MCCR1_BK2_12BITS 0x30 |
| 117 | #define MCCR1_BK3_9BITS 0x00 |
| 118 | #define MCCR1_BK3_10BITS 0x40 |
| 119 | #define MCCR1_BK3_11BITS 0x80 |
| 120 | #define MCCR1_BK3_12BITS 0xC0 |
| 121 | #define MCCR1_MEMGO 0x00080000 |
| 122 | |
| 123 | #define MPC106_MCCR2 0xF4 |
| 124 | #define MPC106_MCCR3 0xF8 |
| 125 | #define MPC106_MCCR4 0xFC |
| 126 | |
| 127 | #define MPC106_MSAR1 0x80 |
| 128 | #define MPC106_EMSAR1 0x88 |
| 129 | #define MPC106_EMSAR2 0x8C |
| 130 | #define MPC106_MEAR1 0x90 |
| 131 | #define MPC106_EMEAR1 0x98 |
| 132 | #define MPC106_EMEAR2 0x9C |
| 133 | |
| 134 | #define MPC106_MBER 0xA0 |
| 135 | #define MBER_BANK0 0x1 |
| 136 | #define MBER_BANK1 0x2 |
| 137 | #define MBER_BANK2 0x4 |
| 138 | #define MBER_BANK3 0x8 |
| 139 | |
| 140 | #endif |