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Vikas Manocha6a12ceb2016-02-11 15:47:19 -08001/*
2 * (C) Copyright 2016
3 * Vikas Manocha, <vikas.manocha@st.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#ifndef _SERIAL_STM32_X7_
9#define _SERIAL_STM32_X7_
10
11struct stm32_usart {
12 u32 cr1;
13 u32 cr2;
14 u32 cr3;
15 u32 brr;
16 u32 gtpr;
17 u32 rtor;
18 u32 rqr;
19 u32 sr;
20 u32 icr;
21 u32 rd_dr;
22 u32 tx_dr;
23};
24
Patrice Chotard122b2d42017-07-18 09:29:07 +020025/* Information about a serial port */
26struct stm32x7_serial_platdata {
27 struct stm32_usart *base; /* address of registers in physical memory */
Patrice Chotard27265ce2017-07-18 09:29:08 +020028 unsigned long int clock_rate;
Patrice Chotard122b2d42017-07-18 09:29:07 +020029};
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080030
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020031#define USART_CR1_OVER8 (1 << 15)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080032#define USART_CR1_TE (1 << 3)
Patrice Chotard1afcf9c2017-06-08 09:26:55 +020033#define USART_CR1_RE (1 << 2)
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080034#define USART_CR1_UE (1 << 0)
35
Vikas Manocha6c0c3ce2017-05-28 12:55:12 -070036#define USART_CR3_OVRDIS (1 << 12)
37
Vikas Manocha6a12ceb2016-02-11 15:47:19 -080038#define USART_SR_FLAG_RXNE (1 << 5)
39#define USART_SR_FLAG_TXE (1 << 7)
40
41#define USART_BRR_F_MASK 0xFF
42#define USART_BRR_M_SHIFT 4
43#define USART_BRR_M_MASK 0xFFF0
44
45#endif