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Tom Rini83d290c2018-05-06 17:58:06 -04001# SPDX-License-Identifier: GPL-2.0+
Jean-Christophe PLAGNIOL-VILLARDc8aa7df2008-10-31 12:26:55 +01002#
3# (C) Copyright 2008
4# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
Jean-Christophe PLAGNIOL-VILLARDc8aa7df2008-10-31 12:26:55 +01005
Masahiro Yamada710f1d32013-10-17 17:34:57 +09006obj-y += fpga.o
Alexander Dahl1323d082022-09-30 14:04:30 +02007obj-$(CONFIG_DM_FPGA) += fpga-uclass.o
8obj-$(CONFIG_SANDBOX_FPGA) += sandbox.o
9
Masahiro Yamada710f1d32013-10-17 17:34:57 +090010obj-$(CONFIG_FPGA_SPARTAN2) += spartan2.o
11obj-$(CONFIG_FPGA_SPARTAN3) += spartan3.o
Siva Durga Prasad Paladugu26e054c2019-08-05 15:54:59 +053012obj-$(CONFIG_FPGA_VERSALPL) += versalpl.o
Masahiro Yamada710f1d32013-10-17 17:34:57 +090013obj-$(CONFIG_FPGA_VIRTEX2) += virtex2.o
14obj-$(CONFIG_FPGA_ZYNQPL) += zynqpl.o
Siva Durga Prasad Paladugu6b245012016-01-13 16:25:37 +053015obj-$(CONFIG_FPGA_ZYNQMPPL) += zynqmppl.o
Masahiro Yamada710f1d32013-10-17 17:34:57 +090016obj-$(CONFIG_FPGA_XILINX) += xilinx.o
17obj-$(CONFIG_FPGA_LATTICE) += ivm_core.o lattice.o
Jean-Christophe PLAGNIOL-VILLARDc8aa7df2008-10-31 12:26:55 +010018ifdef CONFIG_FPGA_ALTERA
Masahiro Yamada710f1d32013-10-17 17:34:57 +090019obj-y += altera.o
20obj-$(CONFIG_FPGA_ACEX1K) += ACEX1K.o
21obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
Chee Hong Angd2170162020-08-07 11:50:03 +080022obj-$(CONFIG_FPGA_INTEL_SDM_MAILBOX) += intel_sdm_mb.o
Masahiro Yamada710f1d32013-10-17 17:34:57 +090023obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
Stefan Roeseff9c4c52016-02-12 13:48:02 +010024obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
Pavel Machek230fe9b2014-09-08 14:08:45 +020025obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
Tien Fong Chee6867e192017-07-26 13:05:38 +080026obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
Tien Fong Chee2baa9972017-07-26 13:05:43 +080027obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
Jean-Christophe PLAGNIOL-VILLARDc8aa7df2008-10-31 12:26:55 +010028endif