blob: 2f433cedd093e23f5638ad603876092a06aa40eb [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Kumar Galac916d7c2011-04-13 08:37:44 -05002/*
Roy Zang111fd192012-10-08 07:44:21 +00003 * Copyright 2009-2012 Freescale Semiconductor, Inc.
Madalin Bucur6eb32a02020-04-23 16:25:19 +03004 * Copyright 2020 NXP
Kumar Galac916d7c2011-04-13 08:37:44 -05005 * Dave Liu <daveliu@freescale.com>
Kumar Galac916d7c2011-04-13 08:37:44 -05006 */
7#include <common.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06008#include <log.h>
Simon Glasse6f6f9e2020-05-10 11:39:58 -06009#include <part.h>
Kumar Galac916d7c2011-04-13 08:37:44 -050010#include <asm/io.h>
Madalin Bucur6eb32a02020-04-23 16:25:19 +030011#ifdef CONFIG_DM_ETH
12#include <dm.h>
13#include <dm/ofnode.h>
14#include <linux/compat.h>
15#include <phy_interface.h>
16#endif
Kumar Galac916d7c2011-04-13 08:37:44 -050017#include <malloc.h>
18#include <net.h>
19#include <hwconfig.h>
20#include <fm_eth.h>
21#include <fsl_mdio.h>
22#include <miiphy.h>
23#include <phy.h>
Shaohui Xie8225b2f2015-10-26 19:47:47 +080024#include <fsl_dtsec.h>
25#include <fsl_tgec.h>
Shaohui Xiecd348ef2015-03-20 19:28:19 -070026#include <fsl_memac.h>
Simon Glassc05ed002020-05-10 11:40:11 -060027#include <linux/delay.h>
Kumar Galac916d7c2011-04-13 08:37:44 -050028
29#include "fm.h"
30
Madalin Bucur6eb32a02020-04-23 16:25:19 +030031#ifndef CONFIG_DM_ETH
Kumar Galac916d7c2011-04-13 08:37:44 -050032static struct eth_device *devlist[NUM_FM_PORTS];
33static int num_controllers;
Madalin Bucur6eb32a02020-04-23 16:25:19 +030034#endif
Kumar Galac916d7c2011-04-13 08:37:44 -050035
36#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) && !defined(BITBANGMII)
37
38#define TBIANA_SETTINGS (TBIANA_ASYMMETRIC_PAUSE | TBIANA_SYMMETRIC_PAUSE | \
39 TBIANA_FULL_DUPLEX)
40
41#define TBIANA_SGMII_ACK 0x4001
42
43#define TBICR_SETTINGS (TBICR_ANEG_ENABLE | TBICR_RESTART_ANEG | \
44 TBICR_FULL_DUPLEX | TBICR_SPEED1_SET)
45
46/* Configure the TBI for SGMII operation */
Kim Phillips960d70c2012-10-29 13:34:34 +000047static void dtsec_configure_serdes(struct fm_eth *priv)
Kumar Galac916d7c2011-04-13 08:37:44 -050048{
Roy Zang111fd192012-10-08 07:44:21 +000049#ifdef CONFIG_SYS_FMAN_V3
50 u32 value;
51 struct mii_dev bus;
Shengzhou Liuc35f8692014-10-23 17:20:57 +080052 bool sgmii_2500 = (priv->enet_if ==
53 PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
Madalin Bucur6eb32a02020-04-23 16:25:19 +030054 int i = 0, j;
55
56#ifndef CONFIG_DM_ETH
57 bus.priv = priv->mac->phyregs;
58#else
59 bus.priv = priv->pcs_mdio;
Madalin Bucur6eb32a02020-04-23 16:25:19 +030060 bus.read = memac_mdio_read;
61 bus.write = memac_mdio_write;
62 bus.reset = memac_mdio_reset;
Madalin Bucur9b2e8922020-05-04 13:09:12 +030063#endif
Roy Zang111fd192012-10-08 07:44:21 +000064
Shaohui Xiebc246112015-10-26 19:47:48 +080065qsgmii_loop:
Shengzhou Liuc35f8692014-10-23 17:20:57 +080066 /* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
shaohui xiebead0882016-11-15 14:36:47 +080067 if (sgmii_2500)
68 value = PHY_SGMII_CR_PHY_RESET |
69 PHY_SGMII_IF_SPEED_GIGABIT |
70 PHY_SGMII_IF_MODE_SGMII;
71 else
72 value = PHY_SGMII_IF_MODE_SGMII | PHY_SGMII_IF_MODE_AN;
Shengzhou Liuc35f8692014-10-23 17:20:57 +080073
Madalin Bucur6eb32a02020-04-23 16:25:19 +030074 for (j = 0; j <= 3; j++)
75 debug("dump PCS reg %#x: %#x\n", j,
76 memac_mdio_read(&bus, i, MDIO_DEVAD_NONE, j));
77
Shaohui Xiebc246112015-10-26 19:47:48 +080078 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x14, value);
Roy Zang111fd192012-10-08 07:44:21 +000079
80 /* Dev ability according to SGMII specification */
81 value = PHY_SGMII_DEV_ABILITY_SGMII;
Shaohui Xiebc246112015-10-26 19:47:48 +080082 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x4, value);
Roy Zang111fd192012-10-08 07:44:21 +000083
shaohui xiebead0882016-11-15 14:36:47 +080084 if (sgmii_2500) {
85 /* Adjust link timer for 2.5G SGMII,
86 * 1.6 ms in units of 3.2 ns:
87 * 1.6ms / 3.2ns = 5 * 10^5 = 0x7a120.
88 */
89 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0007);
90 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0xa120);
91 } else {
92 /* Adjust link timer for SGMII,
93 * 1.6 ms in units of 8 ns:
94 * 1.6ms / 8ns = 2 * 10^5 = 0x30d40.
95 */
96 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x13, 0x0003);
97 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0x12, 0x0d40);
98 }
Roy Zang111fd192012-10-08 07:44:21 +000099
100 /* Restart AN */
shaohui xiebead0882016-11-15 14:36:47 +0800101 value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
Shaohui Xiebc246112015-10-26 19:47:48 +0800102 memac_mdio_write(&bus, i, MDIO_DEVAD_NONE, 0, value);
103
104 if ((priv->enet_if == PHY_INTERFACE_MODE_QSGMII) && (i < 3)) {
105 i++;
106 goto qsgmii_loop;
107 }
Roy Zang111fd192012-10-08 07:44:21 +0000108#else
Kumar Galac916d7c2011-04-13 08:37:44 -0500109 struct dtsec *regs = priv->mac->base;
110 struct tsec_mii_mng *phyregs = priv->mac->phyregs;
111
112 /*
113 * Access TBI PHY registers at given TSEC register offset as
114 * opposed to the register offset used for external PHY accesses
115 */
116 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_TBICON,
117 TBICON_CLK_SELECT);
118 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0, TBI_ANA,
119 TBIANA_SGMII_ACK);
120 tsec_local_mdio_write(phyregs, in_be32(&regs->tbipa), 0,
121 TBI_CR, TBICR_SETTINGS);
Roy Zang111fd192012-10-08 07:44:21 +0000122#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500123}
124
Madalin Bucur8313cb02020-04-23 16:25:16 +0300125static void dtsec_init_phy(struct fm_eth *fm_eth)
Kumar Galac916d7c2011-04-13 08:37:44 -0500126{
Roy Zang111fd192012-10-08 07:44:21 +0000127#ifndef CONFIG_SYS_FMAN_V3
shaohui xie1f3bd3e2012-10-11 20:25:36 +0000128 struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR;
129
Kumar Galac916d7c2011-04-13 08:37:44 -0500130 /* Assign a Physical address to the TBI */
131 out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
Roy Zang111fd192012-10-08 07:44:21 +0000132#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500133
Shengzhou Liuc35f8692014-10-23 17:20:57 +0800134 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
Shaohui Xiebc246112015-10-26 19:47:48 +0800135 fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII ||
Shengzhou Liuc35f8692014-10-23 17:20:57 +0800136 fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
Kumar Galac916d7c2011-04-13 08:37:44 -0500137 dtsec_configure_serdes(fm_eth);
138}
139
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300140#ifndef CONFIG_DM_ETH
Shaohui Xie29d8c812015-10-26 19:47:46 +0800141#ifdef CONFIG_PHYLIB
Madalin Bucur8313cb02020-04-23 16:25:16 +0300142static int tgec_is_fibre(struct fm_eth *fm)
Kumar Galac916d7c2011-04-13 08:37:44 -0500143{
Kumar Galac916d7c2011-04-13 08:37:44 -0500144 char phyopt[20];
145
146 sprintf(phyopt, "fsl_fm%d_xaui_phy", fm->fm_index + 1);
147
148 return hwconfig_arg_cmp(phyopt, "xfi");
149}
150#endif
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300151#endif /* CONFIG_DM_ETH */
Shaohui Xie29d8c812015-10-26 19:47:46 +0800152#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500153
154static u16 muram_readw(u16 *addr)
155{
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800156 ulong base = (ulong)addr & ~0x3UL;
157 u32 val32 = in_be32((void *)base);
Kumar Galac916d7c2011-04-13 08:37:44 -0500158 int byte_pos;
159 u16 ret;
160
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800161 byte_pos = (ulong)addr & 0x3UL;
Kumar Galac916d7c2011-04-13 08:37:44 -0500162 if (byte_pos)
163 ret = (u16)(val32 & 0x0000ffff);
164 else
165 ret = (u16)((val32 & 0xffff0000) >> 16);
166
167 return ret;
168}
169
170static void muram_writew(u16 *addr, u16 val)
171{
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800172 ulong base = (ulong)addr & ~0x3UL;
173 u32 org32 = in_be32((void *)base);
Kumar Galac916d7c2011-04-13 08:37:44 -0500174 u32 val32;
175 int byte_pos;
176
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800177 byte_pos = (ulong)addr & 0x3UL;
Kumar Galac916d7c2011-04-13 08:37:44 -0500178 if (byte_pos)
179 val32 = (org32 & 0xffff0000) | val;
180 else
181 val32 = (org32 & 0x0000ffff) | ((u32)val << 16);
182
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800183 out_be32((void *)base, val32);
Kumar Galac916d7c2011-04-13 08:37:44 -0500184}
185
186static void bmi_rx_port_disable(struct fm_bmi_rx_port *rx_port)
187{
188 int timeout = 1000000;
189
190 clrbits_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_EN);
191
192 /* wait until the rx port is not busy */
193 while ((in_be32(&rx_port->fmbm_rst) & FMBM_RST_BSY) && timeout--)
194 ;
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300195 if (!timeout)
196 printf("%s - timeout\n", __func__);
Kumar Galac916d7c2011-04-13 08:37:44 -0500197}
198
199static void bmi_rx_port_init(struct fm_bmi_rx_port *rx_port)
200{
201 /* set BMI to independent mode, Rx port disable */
202 out_be32(&rx_port->fmbm_rcfg, FMBM_RCFG_IM);
203 /* clear FOF in IM case */
204 out_be32(&rx_port->fmbm_rim, 0);
205 /* Rx frame next engine -RISC */
206 out_be32(&rx_port->fmbm_rfne, NIA_ENG_RISC | NIA_RISC_AC_IM_RX);
207 /* Rx command attribute - no order, MR[3] = 1 */
208 clrbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_ORDER | FMBM_RFCA_MR_MASK);
209 setbits_be32(&rx_port->fmbm_rfca, FMBM_RFCA_MR(4));
210 /* enable Rx statistic counters */
211 out_be32(&rx_port->fmbm_rstc, FMBM_RSTC_EN);
212 /* disable Rx performance counters */
213 out_be32(&rx_port->fmbm_rpc, 0);
214}
215
216static void bmi_tx_port_disable(struct fm_bmi_tx_port *tx_port)
217{
218 int timeout = 1000000;
219
220 clrbits_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_EN);
221
222 /* wait until the tx port is not busy */
223 while ((in_be32(&tx_port->fmbm_tst) & FMBM_TST_BSY) && timeout--)
224 ;
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300225 if (!timeout)
226 printf("%s - timeout\n", __func__);
Kumar Galac916d7c2011-04-13 08:37:44 -0500227}
228
229static void bmi_tx_port_init(struct fm_bmi_tx_port *tx_port)
230{
231 /* set BMI to independent mode, Tx port disable */
232 out_be32(&tx_port->fmbm_tcfg, FMBM_TCFG_IM);
233 /* Tx frame next engine -RISC */
234 out_be32(&tx_port->fmbm_tfne, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
235 out_be32(&tx_port->fmbm_tfene, NIA_ENG_RISC | NIA_RISC_AC_IM_TX);
236 /* Tx command attribute - no order, MR[3] = 1 */
237 clrbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_ORDER | FMBM_TFCA_MR_MASK);
238 setbits_be32(&tx_port->fmbm_tfca, FMBM_TFCA_MR(4));
239 /* enable Tx statistic counters */
240 out_be32(&tx_port->fmbm_tstc, FMBM_TSTC_EN);
241 /* disable Tx performance counters */
242 out_be32(&tx_port->fmbm_tpc, 0);
243}
244
245static int fm_eth_rx_port_parameter_init(struct fm_eth *fm_eth)
246{
247 struct fm_port_global_pram *pram;
248 u32 pram_page_offset;
249 void *rx_bd_ring_base;
250 void *rx_buf_pool;
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800251 u32 bd_ring_base_lo, bd_ring_base_hi;
252 u32 buf_lo, buf_hi;
Kumar Galac916d7c2011-04-13 08:37:44 -0500253 struct fm_port_bd *rxbd;
254 struct fm_port_qd *rxqd;
255 struct fm_bmi_rx_port *bmi_rx_port = fm_eth->rx_port;
256 int i;
257
258 /* alloc global parameter ram at MURAM */
259 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
260 FM_PRAM_SIZE, FM_PRAM_ALIGN);
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800261 if (!pram) {
262 printf("%s: No muram for Rx global parameter\n", __func__);
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800263 return -ENOMEM;
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800264 }
265
Kumar Galac916d7c2011-04-13 08:37:44 -0500266 fm_eth->rx_pram = pram;
267
268 /* parameter page offset to MURAM */
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800269 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
Kumar Galac916d7c2011-04-13 08:37:44 -0500270
271 /* enable global mode- snooping data buffers and BDs */
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800272 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
Kumar Galac916d7c2011-04-13 08:37:44 -0500273
274 /* init the Rx queue descriptor pionter */
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800275 out_be32(&pram->rxqd_ptr, pram_page_offset + 0x20);
Kumar Galac916d7c2011-04-13 08:37:44 -0500276
277 /* set the max receive buffer length, power of 2 */
278 muram_writew(&pram->mrblr, MAX_RXBUF_LOG2);
279
280 /* alloc Rx buffer descriptors from main memory */
281 rx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
282 * RX_BD_RING_SIZE);
283 if (!rx_bd_ring_base)
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800284 return -ENOMEM;
285
Kumar Galac916d7c2011-04-13 08:37:44 -0500286 memset(rx_bd_ring_base, 0, sizeof(struct fm_port_bd)
287 * RX_BD_RING_SIZE);
288
289 /* alloc Rx buffer from main memory */
290 rx_buf_pool = malloc(MAX_RXBUF_LEN * RX_BD_RING_SIZE);
291 if (!rx_buf_pool)
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800292 return -ENOMEM;
293
Kumar Galac916d7c2011-04-13 08:37:44 -0500294 memset(rx_buf_pool, 0, MAX_RXBUF_LEN * RX_BD_RING_SIZE);
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800295 debug("%s: rx_buf_pool = %p\n", __func__, rx_buf_pool);
Kumar Galac916d7c2011-04-13 08:37:44 -0500296
297 /* save them to fm_eth */
298 fm_eth->rx_bd_ring = rx_bd_ring_base;
299 fm_eth->cur_rxbd = rx_bd_ring_base;
300 fm_eth->rx_buf = rx_buf_pool;
301
302 /* init Rx BDs ring */
303 rxbd = (struct fm_port_bd *)rx_bd_ring_base;
304 for (i = 0; i < RX_BD_RING_SIZE; i++) {
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800305 muram_writew(&rxbd->status, RxBD_EMPTY);
306 muram_writew(&rxbd->len, 0);
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800307 buf_hi = upper_32_bits(virt_to_phys(rx_buf_pool +
308 i * MAX_RXBUF_LEN));
309 buf_lo = lower_32_bits(virt_to_phys(rx_buf_pool +
310 i * MAX_RXBUF_LEN));
311 muram_writew(&rxbd->buf_ptr_hi, (u16)buf_hi);
312 out_be32(&rxbd->buf_ptr_lo, buf_lo);
Kumar Galac916d7c2011-04-13 08:37:44 -0500313 rxbd++;
314 }
315
316 /* set the Rx queue descriptor */
317 rxqd = &pram->rxqd;
318 muram_writew(&rxqd->gen, 0);
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800319 bd_ring_base_hi = upper_32_bits(virt_to_phys(rx_bd_ring_base));
320 bd_ring_base_lo = lower_32_bits(virt_to_phys(rx_bd_ring_base));
321 muram_writew(&rxqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
322 out_be32(&rxqd->bd_ring_base_lo, bd_ring_base_lo);
Kumar Galac916d7c2011-04-13 08:37:44 -0500323 muram_writew(&rxqd->bd_ring_size, sizeof(struct fm_port_bd)
324 * RX_BD_RING_SIZE);
325 muram_writew(&rxqd->offset_in, 0);
326 muram_writew(&rxqd->offset_out, 0);
327
328 /* set IM parameter ram pointer to Rx Frame Queue ID */
329 out_be32(&bmi_rx_port->fmbm_rfqid, pram_page_offset);
330
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800331 return 0;
Kumar Galac916d7c2011-04-13 08:37:44 -0500332}
333
334static int fm_eth_tx_port_parameter_init(struct fm_eth *fm_eth)
335{
336 struct fm_port_global_pram *pram;
337 u32 pram_page_offset;
338 void *tx_bd_ring_base;
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800339 u32 bd_ring_base_lo, bd_ring_base_hi;
Kumar Galac916d7c2011-04-13 08:37:44 -0500340 struct fm_port_bd *txbd;
341 struct fm_port_qd *txqd;
342 struct fm_bmi_tx_port *bmi_tx_port = fm_eth->tx_port;
343 int i;
344
345 /* alloc global parameter ram at MURAM */
346 pram = (struct fm_port_global_pram *)fm_muram_alloc(fm_eth->fm_index,
347 FM_PRAM_SIZE, FM_PRAM_ALIGN);
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800348 if (!pram) {
349 printf("%s: No muram for Tx global parameter\n", __func__);
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800350 return -ENOMEM;
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800351 }
Kumar Galac916d7c2011-04-13 08:37:44 -0500352 fm_eth->tx_pram = pram;
353
354 /* parameter page offset to MURAM */
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800355 pram_page_offset = (void *)pram - fm_muram_base(fm_eth->fm_index);
Kumar Galac916d7c2011-04-13 08:37:44 -0500356
357 /* enable global mode- snooping data buffers and BDs */
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800358 out_be32(&pram->mode, PRAM_MODE_GLOBAL);
Kumar Galac916d7c2011-04-13 08:37:44 -0500359
360 /* init the Tx queue descriptor pionter */
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800361 out_be32(&pram->txqd_ptr, pram_page_offset + 0x40);
Kumar Galac916d7c2011-04-13 08:37:44 -0500362
363 /* alloc Tx buffer descriptors from main memory */
364 tx_bd_ring_base = malloc(sizeof(struct fm_port_bd)
365 * TX_BD_RING_SIZE);
366 if (!tx_bd_ring_base)
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800367 return -ENOMEM;
368
Kumar Galac916d7c2011-04-13 08:37:44 -0500369 memset(tx_bd_ring_base, 0, sizeof(struct fm_port_bd)
370 * TX_BD_RING_SIZE);
371 /* save it to fm_eth */
372 fm_eth->tx_bd_ring = tx_bd_ring_base;
373 fm_eth->cur_txbd = tx_bd_ring_base;
374
375 /* init Tx BDs ring */
376 txbd = (struct fm_port_bd *)tx_bd_ring_base;
377 for (i = 0; i < TX_BD_RING_SIZE; i++) {
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800378 muram_writew(&txbd->status, TxBD_LAST);
379 muram_writew(&txbd->len, 0);
380 muram_writew(&txbd->buf_ptr_hi, 0);
381 out_be32(&txbd->buf_ptr_lo, 0);
382 txbd++;
Kumar Galac916d7c2011-04-13 08:37:44 -0500383 }
384
385 /* set the Tx queue decriptor */
386 txqd = &pram->txqd;
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800387 bd_ring_base_hi = upper_32_bits(virt_to_phys(tx_bd_ring_base));
388 bd_ring_base_lo = lower_32_bits(virt_to_phys(tx_bd_ring_base));
389 muram_writew(&txqd->bd_ring_base_hi, (u16)bd_ring_base_hi);
390 out_be32(&txqd->bd_ring_base_lo, bd_ring_base_lo);
Kumar Galac916d7c2011-04-13 08:37:44 -0500391 muram_writew(&txqd->bd_ring_size, sizeof(struct fm_port_bd)
392 * TX_BD_RING_SIZE);
393 muram_writew(&txqd->offset_in, 0);
394 muram_writew(&txqd->offset_out, 0);
395
396 /* set IM parameter ram pointer to Tx Confirmation Frame Queue ID */
397 out_be32(&bmi_tx_port->fmbm_tcfqid, pram_page_offset);
398
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800399 return 0;
Kumar Galac916d7c2011-04-13 08:37:44 -0500400}
401
402static int fm_eth_init(struct fm_eth *fm_eth)
403{
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800404 int ret;
Kumar Galac916d7c2011-04-13 08:37:44 -0500405
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800406 ret = fm_eth_rx_port_parameter_init(fm_eth);
407 if (ret)
408 return ret;
Kumar Galac916d7c2011-04-13 08:37:44 -0500409
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800410 ret = fm_eth_tx_port_parameter_init(fm_eth);
411 if (ret)
412 return ret;
Kumar Galac916d7c2011-04-13 08:37:44 -0500413
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800414 return 0;
Kumar Galac916d7c2011-04-13 08:37:44 -0500415}
416
417static int fm_eth_startup(struct fm_eth *fm_eth)
418{
419 struct fsl_enet_mac *mac;
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800420 int ret;
421
Kumar Galac916d7c2011-04-13 08:37:44 -0500422 mac = fm_eth->mac;
423
424 /* Rx/TxBDs, Rx/TxQDs, Rx buff and parameter ram init */
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800425 ret = fm_eth_init(fm_eth);
426 if (ret)
427 return ret;
Kumar Galac916d7c2011-04-13 08:37:44 -0500428 /* setup the MAC controller */
429 mac->init_mac(mac);
430
431 /* For some reason we need to set SPEED_100 */
Shaohui Xie1c68d012013-08-19 18:58:52 +0800432 if (((fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII) ||
shaohui xiebead0882016-11-15 14:36:47 +0800433 (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500) ||
Shaohui Xie1c68d012013-08-19 18:58:52 +0800434 (fm_eth->enet_if == PHY_INTERFACE_MODE_QSGMII)) &&
435 mac->set_if_mode)
Kumar Galac916d7c2011-04-13 08:37:44 -0500436 mac->set_if_mode(mac, fm_eth->enet_if, SPEED_100);
437
438 /* init bmi rx port, IM mode and disable */
439 bmi_rx_port_init(fm_eth->rx_port);
440 /* init bmi tx port, IM mode and disable */
441 bmi_tx_port_init(fm_eth->tx_port);
442
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800443 return 0;
Kumar Galac916d7c2011-04-13 08:37:44 -0500444}
445
446static void fmc_tx_port_graceful_stop_enable(struct fm_eth *fm_eth)
447{
448 struct fm_port_global_pram *pram;
449
450 pram = fm_eth->tx_pram;
451 /* graceful stop transmission of frames */
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800452 setbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
Kumar Galac916d7c2011-04-13 08:37:44 -0500453 sync();
454}
455
456static void fmc_tx_port_graceful_stop_disable(struct fm_eth *fm_eth)
457{
458 struct fm_port_global_pram *pram;
459
460 pram = fm_eth->tx_pram;
461 /* re-enable transmission of frames */
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800462 clrbits_be32(&pram->mode, PRAM_MODE_GRACEFUL_STOP);
Kumar Galac916d7c2011-04-13 08:37:44 -0500463 sync();
464}
465
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300466#ifndef CONFIG_DM_ETH
Masahiro Yamadab75d8dc2020-06-26 15:13:33 +0900467static int fm_eth_open(struct eth_device *dev, struct bd_info *bd)
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300468#else
469static int fm_eth_open(struct udevice *dev)
470#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500471{
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300472#ifndef CONFIG_DM_ETH
473 struct fm_eth *fm_eth = dev->priv;
474#else
475 struct eth_pdata *pdata = dev_get_platdata(dev);
476 struct fm_eth *fm_eth = dev_get_priv(dev);
477#endif
478 unsigned char *enetaddr;
Kumar Galac916d7c2011-04-13 08:37:44 -0500479 struct fsl_enet_mac *mac;
Timur Tabi11af8d62012-07-09 08:52:43 +0000480#ifdef CONFIG_PHYLIB
481 int ret;
482#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500483
Kumar Galac916d7c2011-04-13 08:37:44 -0500484 mac = fm_eth->mac;
485
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300486#ifndef CONFIG_DM_ETH
487 enetaddr = &dev->enetaddr[0];
488#else
489 enetaddr = pdata->enetaddr;
490#endif
491
Kumar Galac916d7c2011-04-13 08:37:44 -0500492 /* setup the MAC address */
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300493 if (enetaddr[0] & 0x01) {
494 printf("%s: MacAddress is multicast address\n", __func__);
495 enetaddr[0] = 0;
496 enetaddr[5] = fm_eth->num;
Kumar Galac916d7c2011-04-13 08:37:44 -0500497 }
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300498 mac->set_mac_addr(mac, enetaddr);
Kumar Galac916d7c2011-04-13 08:37:44 -0500499
500 /* enable bmi Rx port */
501 setbits_be32(&fm_eth->rx_port->fmbm_rcfg, FMBM_RCFG_EN);
502 /* enable MAC rx/tx port */
503 mac->enable_mac(mac);
504 /* enable bmi Tx port */
505 setbits_be32(&fm_eth->tx_port->fmbm_tcfg, FMBM_TCFG_EN);
506 /* re-enable transmission of frame */
507 fmc_tx_port_graceful_stop_disable(fm_eth);
508
509#ifdef CONFIG_PHYLIB
Codrin Ciubotariu6798c322015-01-12 14:08:29 +0200510 if (fm_eth->phydev) {
511 ret = phy_startup(fm_eth->phydev);
512 if (ret) {
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300513#ifndef CONFIG_DM_ETH
Codrin Ciubotariu6798c322015-01-12 14:08:29 +0200514 printf("%s: Could not initialize\n",
515 fm_eth->phydev->dev->name);
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300516#else
517 printf("%s: Could not initialize\n", dev->name);
518#endif
Codrin Ciubotariu6798c322015-01-12 14:08:29 +0200519 return ret;
520 }
521 } else {
522 return 0;
Timur Tabi11af8d62012-07-09 08:52:43 +0000523 }
Kumar Galac916d7c2011-04-13 08:37:44 -0500524#else
525 fm_eth->phydev->speed = SPEED_1000;
526 fm_eth->phydev->link = 1;
527 fm_eth->phydev->duplex = DUPLEX_FULL;
528#endif
529
530 /* set the MAC-PHY mode */
531 mac->set_if_mode(mac, fm_eth->enet_if, fm_eth->phydev->speed);
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300532 debug("MAC IF mode %d, speed %d, link %d\n", fm_eth->enet_if,
533 fm_eth->phydev->speed, fm_eth->phydev->link);
Kumar Galac916d7c2011-04-13 08:37:44 -0500534
535 if (!fm_eth->phydev->link)
536 printf("%s: No link.\n", fm_eth->phydev->dev->name);
537
538 return fm_eth->phydev->link ? 0 : -1;
539}
540
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300541#ifndef CONFIG_DM_ETH
Kumar Galac916d7c2011-04-13 08:37:44 -0500542static void fm_eth_halt(struct eth_device *dev)
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300543#else
544static void fm_eth_halt(struct udevice *dev)
545#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500546{
547 struct fm_eth *fm_eth;
548 struct fsl_enet_mac *mac;
549
550 fm_eth = (struct fm_eth *)dev->priv;
551 mac = fm_eth->mac;
552
553 /* graceful stop the transmission of frames */
554 fmc_tx_port_graceful_stop_enable(fm_eth);
555 /* disable bmi Tx port */
556 bmi_tx_port_disable(fm_eth->tx_port);
557 /* disable MAC rx/tx port */
558 mac->disable_mac(mac);
559 /* disable bmi Rx port */
560 bmi_rx_port_disable(fm_eth->rx_port);
561
Shaohui Xie29d8c812015-10-26 19:47:46 +0800562#ifdef CONFIG_PHYLIB
Codrin Ciubotariu6798c322015-01-12 14:08:29 +0200563 if (fm_eth->phydev)
564 phy_shutdown(fm_eth->phydev);
Shaohui Xie29d8c812015-10-26 19:47:46 +0800565#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500566}
567
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300568#ifndef CONFIG_DM_ETH
Joe Hershbergere9df2012012-05-22 07:56:15 +0000569static int fm_eth_send(struct eth_device *dev, void *buf, int len)
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300570#else
571static int fm_eth_send(struct udevice *dev, void *buf, int len)
572#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500573{
574 struct fm_eth *fm_eth;
575 struct fm_port_global_pram *pram;
576 struct fm_port_bd *txbd, *txbd_base;
577 u16 offset_in;
578 int i;
579
580 fm_eth = (struct fm_eth *)dev->priv;
581 pram = fm_eth->tx_pram;
582 txbd = fm_eth->cur_txbd;
583
584 /* find one empty TxBD */
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800585 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
Kumar Galac916d7c2011-04-13 08:37:44 -0500586 udelay(100);
587 if (i > 0x1000) {
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800588 printf("%s: Tx buffer not ready, txbd->status = 0x%x\n",
589 dev->name, muram_readw(&txbd->status));
Kumar Galac916d7c2011-04-13 08:37:44 -0500590 return 0;
591 }
592 }
593 /* setup TxBD */
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800594 muram_writew(&txbd->buf_ptr_hi, (u16)upper_32_bits(virt_to_phys(buf)));
595 out_be32(&txbd->buf_ptr_lo, lower_32_bits(virt_to_phys(buf)));
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800596 muram_writew(&txbd->len, len);
Kumar Galac916d7c2011-04-13 08:37:44 -0500597 sync();
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800598 muram_writew(&txbd->status, TxBD_READY | TxBD_LAST);
Kumar Galac916d7c2011-04-13 08:37:44 -0500599 sync();
600
601 /* update TxQD, let RISC to send the packet */
602 offset_in = muram_readw(&pram->txqd.offset_in);
603 offset_in += sizeof(struct fm_port_bd);
604 if (offset_in >= muram_readw(&pram->txqd.bd_ring_size))
605 offset_in = 0;
606 muram_writew(&pram->txqd.offset_in, offset_in);
607 sync();
608
609 /* wait for buffer to be transmitted */
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800610 for (i = 0; muram_readw(&txbd->status) & TxBD_READY; i++) {
Kumar Galac916d7c2011-04-13 08:37:44 -0500611 udelay(100);
612 if (i > 0x10000) {
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800613 printf("%s: Tx error, txbd->status = 0x%x\n",
614 dev->name, muram_readw(&txbd->status));
Kumar Galac916d7c2011-04-13 08:37:44 -0500615 return 0;
616 }
617 }
618
619 /* advance the TxBD */
620 txbd++;
621 txbd_base = (struct fm_port_bd *)fm_eth->tx_bd_ring;
622 if (txbd >= (txbd_base + TX_BD_RING_SIZE))
623 txbd = txbd_base;
624 /* update current txbd */
625 fm_eth->cur_txbd = (void *)txbd;
626
627 return 1;
628}
629
Madalin Bucur1c710182020-04-23 16:25:17 +0300630static struct fm_port_bd *fm_eth_free_one(struct fm_eth *fm_eth,
631 struct fm_port_bd *rxbd)
632{
633 struct fm_port_global_pram *pram;
634 struct fm_port_bd *rxbd_base;
635 u16 offset_out;
636
637 pram = fm_eth->rx_pram;
638
639 /* clear the RxBDs */
640 muram_writew(&rxbd->status, RxBD_EMPTY);
641 muram_writew(&rxbd->len, 0);
642 sync();
643
644 /* advance RxBD */
645 rxbd++;
646 rxbd_base = (struct fm_port_bd *)fm_eth->rx_bd_ring;
647 if (rxbd >= (rxbd_base + RX_BD_RING_SIZE))
648 rxbd = rxbd_base;
649
650 /* update RxQD */
651 offset_out = muram_readw(&pram->rxqd.offset_out);
652 offset_out += sizeof(struct fm_port_bd);
653 if (offset_out >= muram_readw(&pram->rxqd.bd_ring_size))
654 offset_out = 0;
655 muram_writew(&pram->rxqd.offset_out, offset_out);
656 sync();
657
658 return rxbd;
659}
660
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300661#ifndef CONFIG_DM_ETH
Kumar Galac916d7c2011-04-13 08:37:44 -0500662static int fm_eth_recv(struct eth_device *dev)
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300663#else
664static int fm_eth_recv(struct udevice *dev, int flags, uchar **packetp)
665#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500666{
Madalin Bucur1c710182020-04-23 16:25:17 +0300667 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
668 struct fm_port_bd *rxbd = fm_eth->cur_rxbd;
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800669 u32 buf_lo, buf_hi;
Madalin Bucur1c710182020-04-23 16:25:17 +0300670 u16 status, len;
671 int ret = -1;
Kumar Galac916d7c2011-04-13 08:37:44 -0500672 u8 *data;
Kumar Galac916d7c2011-04-13 08:37:44 -0500673
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800674 status = muram_readw(&rxbd->status);
Kumar Galac916d7c2011-04-13 08:37:44 -0500675
676 while (!(status & RxBD_EMPTY)) {
677 if (!(status & RxBD_ERROR)) {
Hou Zhiqiang9fc29db2015-10-26 19:47:44 +0800678 buf_hi = muram_readw(&rxbd->buf_ptr_hi);
679 buf_lo = in_be32(&rxbd->buf_ptr_lo);
680 data = (u8 *)((ulong)(buf_hi << 16) << 16 | buf_lo);
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800681 len = muram_readw(&rxbd->len);
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300682#ifndef CONFIG_DM_ETH
Joe Hershberger1fd92db2015-04-08 01:41:06 -0500683 net_process_received_packet(data, len);
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300684#else
685 *packetp = data;
686 return len;
687#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500688 } else {
689 printf("%s: Rx error\n", dev->name);
Daniel Inderbitzin466f7752015-07-10 14:06:02 +0200690 ret = 0;
Kumar Galac916d7c2011-04-13 08:37:44 -0500691 }
692
Madalin Bucur1c710182020-04-23 16:25:17 +0300693 /* free current bd, advance to next one */
694 rxbd = fm_eth_free_one(fm_eth, rxbd);
Kumar Galac916d7c2011-04-13 08:37:44 -0500695
Kumar Galac916d7c2011-04-13 08:37:44 -0500696 /* read next status */
Hou Zhiqiang648bde62015-10-26 19:47:43 +0800697 status = muram_readw(&rxbd->status);
Kumar Galac916d7c2011-04-13 08:37:44 -0500698 }
699 fm_eth->cur_rxbd = (void *)rxbd;
700
Daniel Inderbitzin466f7752015-07-10 14:06:02 +0200701 return ret;
Kumar Galac916d7c2011-04-13 08:37:44 -0500702}
703
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300704#ifdef CONFIG_DM_ETH
705static int fm_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
706{
707 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
708
709 fm_eth->cur_rxbd = fm_eth_free_one(fm_eth, fm_eth->cur_rxbd);
710
711 return 0;
712}
713#endif /* CONFIG_DM_ETH */
714
715#ifndef CONFIG_DM_ETH
Kumar Galac916d7c2011-04-13 08:37:44 -0500716static int fm_eth_init_mac(struct fm_eth *fm_eth, struct ccsr_fman *reg)
717{
718 struct fsl_enet_mac *mac;
719 int num;
720 void *base, *phyregs = NULL;
721
722 num = fm_eth->num;
723
Roy Zang111fd192012-10-08 07:44:21 +0000724#ifdef CONFIG_SYS_FMAN_V3
Shengzhou Liucc19c252014-11-24 17:11:57 +0800725#ifndef CONFIG_FSL_FM_10GEC_REGULAR_NOTATION
Shengzhou Liu82a55c12013-11-22 17:39:09 +0800726 if (fm_eth->type == FM_ETH_10G_E) {
Shengzhou Liucc19c252014-11-24 17:11:57 +0800727 /* 10GEC1/10GEC2 use mEMAC9/mEMAC10 on T2080/T4240.
728 * 10GEC3/10GEC4 use mEMAC1/mEMAC2 on T2080.
729 * 10GEC1 uses mEMAC1 on T1024.
Shengzhou Liu82a55c12013-11-22 17:39:09 +0800730 * so it needs to change the num.
731 */
732 if (fm_eth->num >= 2)
733 num -= 2;
734 else
735 num += 8;
736 }
Shengzhou Liucc19c252014-11-24 17:11:57 +0800737#endif
Roy Zang111fd192012-10-08 07:44:21 +0000738 base = &reg->memac[num].fm_memac;
739 phyregs = &reg->memac[num].fm_memac_mdio;
740#else
Kumar Galac916d7c2011-04-13 08:37:44 -0500741 /* Get the mac registers base address */
742 if (fm_eth->type == FM_ETH_1G_E) {
743 base = &reg->mac_1g[num].fm_dtesc;
Timur Tabi30381712011-10-04 16:44:43 -0500744 phyregs = &reg->mac_1g[num].fm_mdio.miimcfg;
Kumar Galac916d7c2011-04-13 08:37:44 -0500745 } else {
746 base = &reg->mac_10g[num].fm_10gec;
747 phyregs = &reg->mac_10g[num].fm_10gec_mdio;
748 }
Roy Zang111fd192012-10-08 07:44:21 +0000749#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500750
751 /* alloc mac controller */
752 mac = malloc(sizeof(struct fsl_enet_mac));
753 if (!mac)
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800754 return -ENOMEM;
Kumar Galac916d7c2011-04-13 08:37:44 -0500755 memset(mac, 0, sizeof(struct fsl_enet_mac));
756
757 /* save the mac to fm_eth struct */
758 fm_eth->mac = mac;
759
Roy Zang111fd192012-10-08 07:44:21 +0000760#ifdef CONFIG_SYS_FMAN_V3
761 init_memac(mac, base, phyregs, MAX_RXBUF_LEN);
762#else
Kumar Galac916d7c2011-04-13 08:37:44 -0500763 if (fm_eth->type == FM_ETH_1G_E)
Timur Tabi30381712011-10-04 16:44:43 -0500764 init_dtsec(mac, base, phyregs, MAX_RXBUF_LEN);
Kumar Galac916d7c2011-04-13 08:37:44 -0500765 else
766 init_tgec(mac, base, phyregs, MAX_RXBUF_LEN);
Roy Zang111fd192012-10-08 07:44:21 +0000767#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500768
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800769 return 0;
Kumar Galac916d7c2011-04-13 08:37:44 -0500770}
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300771#else /* CONFIG_DM_ETH */
772static int fm_eth_init_mac(struct fm_eth *fm_eth, void *reg)
773{
774#ifndef CONFIG_SYS_FMAN_V3
775 void *mdio;
776#endif
777
778 fm_eth->mac = kzalloc(sizeof(*fm_eth->mac), GFP_KERNEL);
779 if (!fm_eth->mac)
780 return -ENOMEM;
781
782#ifndef CONFIG_SYS_FMAN_V3
783 mdio = fman_mdio(fm_eth->dev->parent, fm_eth->mac_type, fm_eth->num);
784 debug("MDIO %d @ %p\n", fm_eth->num, mdio);
785#endif
786
787 switch (fm_eth->mac_type) {
788#ifdef CONFIG_SYS_FMAN_V3
789 case FM_MEMAC:
790 init_memac(fm_eth->mac, reg, NULL, MAX_RXBUF_LEN);
791 break;
792#else
793 case FM_DTSEC:
794 init_dtsec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
795 break;
796 case FM_TGEC:
797 init_tgec(fm_eth->mac, reg, mdio, MAX_RXBUF_LEN);
798 break;
799#endif
800 }
801
802 return 0;
803}
804#endif /* CONFIG_DM_ETH */
Kumar Galac916d7c2011-04-13 08:37:44 -0500805
Madalin Bucur8313cb02020-04-23 16:25:16 +0300806static int init_phy(struct fm_eth *fm_eth)
Kumar Galac916d7c2011-04-13 08:37:44 -0500807{
Shaohui Xie29d8c812015-10-26 19:47:46 +0800808#ifdef CONFIG_PHYLIB
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300809 u32 supported = PHY_GBIT_FEATURES;
810#ifndef CONFIG_DM_ETH
Kumar Galac916d7c2011-04-13 08:37:44 -0500811 struct phy_device *phydev = NULL;
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300812#endif
813
814 if (fm_eth->type == FM_ETH_10G_E)
815 supported = PHY_10G_FEATURES;
816 if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
817 supported |= SUPPORTED_2500baseX_Full;
Shaohui Xie29d8c812015-10-26 19:47:46 +0800818#endif
Kumar Galac916d7c2011-04-13 08:37:44 -0500819
Kumar Galac916d7c2011-04-13 08:37:44 -0500820 if (fm_eth->type == FM_ETH_1G_E)
Madalin Bucur8313cb02020-04-23 16:25:16 +0300821 dtsec_init_phy(fm_eth);
Kumar Galac916d7c2011-04-13 08:37:44 -0500822
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300823#ifdef CONFIG_DM_ETH
824#ifdef CONFIG_PHYLIB
825#ifdef CONFIG_DM_MDIO
826 fm_eth->phydev = dm_eth_phy_connect(fm_eth->dev);
827 if (!fm_eth->phydev)
828 return -ENODEV;
829#endif
830 fm_eth->phydev->advertising &= supported;
831 fm_eth->phydev->supported &= supported;
832
833 phy_config(fm_eth->phydev);
834#endif
835#else /* CONFIG_DM_ETH */
Shaohui Xie29d8c812015-10-26 19:47:46 +0800836#ifdef CONFIG_PHYLIB
Kumar Galac916d7c2011-04-13 08:37:44 -0500837 if (fm_eth->bus) {
Madalin Bucur8313cb02020-04-23 16:25:16 +0300838 phydev = phy_connect(fm_eth->bus, fm_eth->phyaddr, fm_eth->dev,
839 fm_eth->enet_if);
Codrin Ciubotariu6798c322015-01-12 14:08:29 +0200840 if (!phydev) {
841 printf("Failed to connect\n");
842 return -1;
843 }
844 } else {
845 return 0;
Kumar Galac916d7c2011-04-13 08:37:44 -0500846 }
847
848 if (fm_eth->type == FM_ETH_1G_E) {
849 supported = (SUPPORTED_10baseT_Half |
850 SUPPORTED_10baseT_Full |
851 SUPPORTED_100baseT_Half |
852 SUPPORTED_100baseT_Full |
853 SUPPORTED_1000baseT_Full);
854 } else {
855 supported = SUPPORTED_10000baseT_Full;
856
Madalin Bucur8313cb02020-04-23 16:25:16 +0300857 if (tgec_is_fibre(fm_eth))
Kumar Galac916d7c2011-04-13 08:37:44 -0500858 phydev->port = PORT_FIBRE;
859 }
860
861 phydev->supported &= supported;
862 phydev->advertising = phydev->supported;
863
864 fm_eth->phydev = phydev;
865
866 phy_config(phydev);
867#endif
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300868#endif /* CONFIG_DM_ETH */
Kumar Galac916d7c2011-04-13 08:37:44 -0500869 return 0;
870}
871
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300872#ifndef CONFIG_DM_ETH
Kumar Galac916d7c2011-04-13 08:37:44 -0500873int fm_eth_initialize(struct ccsr_fman *reg, struct fm_eth_info *info)
874{
875 struct eth_device *dev;
876 struct fm_eth *fm_eth;
877 int i, num = info->num;
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800878 int ret;
Kumar Galac916d7c2011-04-13 08:37:44 -0500879
880 /* alloc eth device */
881 dev = (struct eth_device *)malloc(sizeof(struct eth_device));
882 if (!dev)
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800883 return -ENOMEM;
Kumar Galac916d7c2011-04-13 08:37:44 -0500884 memset(dev, 0, sizeof(struct eth_device));
885
886 /* alloc the FMan ethernet private struct */
887 fm_eth = (struct fm_eth *)malloc(sizeof(struct fm_eth));
888 if (!fm_eth)
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800889 return -ENOMEM;
Kumar Galac916d7c2011-04-13 08:37:44 -0500890 memset(fm_eth, 0, sizeof(struct fm_eth));
891
892 /* save off some things we need from the info struct */
893 fm_eth->fm_index = info->index - 1; /* keep as 0 based for muram */
894 fm_eth->num = num;
895 fm_eth->type = info->type;
896
897 fm_eth->rx_port = (void *)&reg->port[info->rx_port_id - 1].fm_bmi;
898 fm_eth->tx_port = (void *)&reg->port[info->tx_port_id - 1].fm_bmi;
899
900 /* set the ethernet max receive length */
901 fm_eth->max_rx_len = MAX_RXBUF_LEN;
902
903 /* init global mac structure */
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800904 ret = fm_eth_init_mac(fm_eth, reg);
905 if (ret)
906 return ret;
Kumar Galac916d7c2011-04-13 08:37:44 -0500907
908 /* keep same as the manual, we call FMAN1, FMAN2, DTSEC1, DTSEC2, etc */
909 if (fm_eth->type == FM_ETH_1G_E)
910 sprintf(dev->name, "FM%d@DTSEC%d", info->index, num + 1);
911 else
912 sprintf(dev->name, "FM%d@TGEC%d", info->index, num + 1);
913
914 devlist[num_controllers++] = dev;
915 dev->iobase = 0;
916 dev->priv = (void *)fm_eth;
917 dev->init = fm_eth_open;
918 dev->halt = fm_eth_halt;
919 dev->send = fm_eth_send;
920 dev->recv = fm_eth_recv;
921 fm_eth->dev = dev;
922 fm_eth->bus = info->bus;
923 fm_eth->phyaddr = info->phy_addr;
924 fm_eth->enet_if = info->enet_if;
925
926 /* startup the FM im */
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800927 ret = fm_eth_startup(fm_eth);
928 if (ret)
929 return ret;
Kumar Galac916d7c2011-04-13 08:37:44 -0500930
Madalin Bucur8313cb02020-04-23 16:25:16 +0300931 init_phy(fm_eth);
Kumar Galac916d7c2011-04-13 08:37:44 -0500932
933 /* clear the ethernet address */
934 for (i = 0; i < 6; i++)
935 dev->enetaddr[i] = 0;
936 eth_register(dev);
937
Hou Zhiqiang0f2cb9f2015-10-26 19:47:45 +0800938 return 0;
Kumar Galac916d7c2011-04-13 08:37:44 -0500939}
Madalin Bucur6eb32a02020-04-23 16:25:19 +0300940#else /* CONFIG_DM_ETH */
941#ifdef CONFIG_PHYLIB
942phy_interface_t fman_read_sys_if(struct udevice *dev)
943{
944 const char *if_str;
945
946 if_str = ofnode_read_string(dev->node, "phy-connection-type");
947 debug("MAC system interface mode %s\n", if_str);
948
949 return phy_get_interface_by_name(if_str);
950}
951#endif
952
953static int fm_eth_bind(struct udevice *dev)
954{
955 char mac_name[11];
956 u32 fm, num;
957
958 if (ofnode_read_u32(ofnode_get_parent(dev->node), "cell-index", &fm)) {
959 printf("FMan node property cell-index missing\n");
960 return -EINVAL;
961 }
962
963 if (dev && dev_read_u32(dev, "cell-index", &num)) {
964 printf("FMan MAC node property cell-index missing\n");
965 return -EINVAL;
966 }
967
968 sprintf(mac_name, "fm%d-mac%d", fm + 1, num + 1);
969 device_set_name(dev, mac_name);
970
971 debug("%s - binding %s\n", __func__, mac_name);
972
973 return 0;
974}
975
976static struct udevice *fm_get_internal_mdio(struct udevice *dev)
977{
978 struct ofnode_phandle_args phandle = {.node = ofnode_null()};
979 struct udevice *mdiodev;
980
981 if (dev_read_phandle_with_args(dev, "pcsphy-handle", NULL,
982 0, 0, &phandle) ||
983 !ofnode_valid(phandle.node)) {
984 if (dev_read_phandle_with_args(dev, "tbi-handle", NULL,
985 0, 0, &phandle) ||
986 !ofnode_valid(phandle.node)) {
987 printf("Issue reading pcsphy-handle/tbi-handle for MAC %s\n",
988 dev->name);
989 return NULL;
990 }
991 }
992
993 if (uclass_get_device_by_ofnode(UCLASS_MDIO,
994 ofnode_get_parent(phandle.node),
995 &mdiodev)) {
996 printf("can't find MDIO bus for node %s\n",
997 ofnode_get_name(ofnode_get_parent(phandle.node)));
998 return NULL;
999 }
1000 debug("Found internal MDIO bus %p\n", mdiodev);
1001
1002 return mdiodev;
1003}
1004
1005static int fm_eth_probe(struct udevice *dev)
1006{
1007 struct fm_eth *fm_eth = (struct fm_eth *)dev->priv;
1008 struct ofnode_phandle_args args;
1009 void *reg;
1010 int ret, index;
1011
1012 debug("%s enter for dev %p fm_eth %p - %s\n", __func__, dev, fm_eth,
1013 (dev) ? dev->name : "-");
1014
1015 if (fm_eth->dev) {
1016 printf("%s already probed, exit\n", (dev) ? dev->name : "-");
1017 return 0;
1018 }
1019
1020 fm_eth->dev = dev;
1021 fm_eth->fm_index = fman_id(dev->parent);
1022 reg = (void *)(uintptr_t)dev_read_addr(dev);
1023 fm_eth->mac_type = dev_get_driver_data(dev);
1024#ifdef CONFIG_PHYLIB
1025 fm_eth->enet_if = fman_read_sys_if(dev);
1026#else
1027 fm_eth->enet_if = PHY_INTERFACE_MODE_SGMII;
1028 printf("%s: warning - unable to determine interface type\n", __func__);
1029#endif
1030 switch (fm_eth->mac_type) {
1031#ifndef CONFIG_SYS_FMAN_V3
1032 case FM_TGEC:
1033 fm_eth->type = FM_ETH_10G_E;
1034 break;
1035 case FM_DTSEC:
1036#else
1037 case FM_MEMAC:
1038 /* default to 1G, 10G is indicated by port property in dts */
1039#endif
1040 fm_eth->type = FM_ETH_1G_E;
1041 break;
1042 }
1043
1044 if (dev_read_u32(dev, "cell-index", &fm_eth->num)) {
1045 printf("FMan MAC node property cell-index missing\n");
1046 return -EINVAL;
1047 }
1048
1049 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1050 0, 0, &args))
1051 goto ports_ref_failure;
1052 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1053 if (index <= 0)
1054 goto ports_ref_failure;
1055 fm_eth->rx_port = fman_port(dev->parent, index);
1056
1057 if (ofnode_read_bool(args.node, "fsl,fman-10g-port"))
1058 fm_eth->type = FM_ETH_10G_E;
1059
1060 if (dev_read_phandle_with_args(dev, "fsl,fman-ports", NULL,
1061 0, 1, &args))
1062 goto ports_ref_failure;
1063 index = ofnode_read_u32_default(args.node, "cell-index", 0);
1064 if (index <= 0)
1065 goto ports_ref_failure;
1066 fm_eth->tx_port = fman_port(dev->parent, index);
1067
1068 /* set the ethernet max receive length */
1069 fm_eth->max_rx_len = MAX_RXBUF_LEN;
1070
1071 switch (fm_eth->enet_if) {
1072 case PHY_INTERFACE_MODE_QSGMII:
1073 /* all PCS blocks are accessed on one controller */
1074 if (fm_eth->num != 0)
1075 break;
1076 case PHY_INTERFACE_MODE_SGMII:
1077 case PHY_INTERFACE_MODE_SGMII_2500:
1078 fm_eth->pcs_mdio = fm_get_internal_mdio(dev);
1079 break;
1080 default:
1081 break;
1082 }
1083
1084 /* init global mac structure */
1085 ret = fm_eth_init_mac(fm_eth, reg);
1086 if (ret)
1087 return ret;
1088
1089 /* startup the FM im */
1090 ret = fm_eth_startup(fm_eth);
1091
1092 if (!ret)
1093 ret = init_phy(fm_eth);
1094
1095 return ret;
1096
1097ports_ref_failure:
1098 printf("Issue reading fsl,fman-ports for MAC %s\n", dev->name);
1099 return -ENOENT;
1100}
1101
1102static int fm_eth_remove(struct udevice *dev)
1103{
1104 return 0;
1105}
1106
1107static const struct eth_ops fm_eth_ops = {
1108 .start = fm_eth_open,
1109 .send = fm_eth_send,
1110 .recv = fm_eth_recv,
1111 .free_pkt = fm_eth_free_pkt,
1112 .stop = fm_eth_halt,
1113};
1114
1115static const struct udevice_id fm_eth_ids[] = {
1116#ifdef CONFIG_SYS_FMAN_V3
1117 { .compatible = "fsl,fman-memac", .data = FM_MEMAC },
1118#else
1119 { .compatible = "fsl,fman-dtsec", .data = FM_DTSEC },
1120 { .compatible = "fsl,fman-xgec", .data = FM_TGEC },
1121#endif
1122 {}
1123};
1124
1125U_BOOT_DRIVER(eth_fman) = {
1126 .name = "eth_fman",
1127 .id = UCLASS_ETH,
1128 .of_match = fm_eth_ids,
1129 .bind = fm_eth_bind,
1130 .probe = fm_eth_probe,
1131 .remove = fm_eth_remove,
1132 .ops = &fm_eth_ops,
1133 .priv_auto_alloc_size = sizeof(struct fm_eth),
1134 .platdata_auto_alloc_size = sizeof(struct eth_pdata),
1135 .flags = DM_FLAG_ALLOC_PRIV_DMA,
1136};
1137#endif /* CONFIG_DM_ETH */