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Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04001/*
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +00002 * Common configuration settings for IGEP technology based boards
3 *
4 * (C) Copyright 2012
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04005 * ISEE 2007 SL, <www.iseebcn.com>
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -04008 */
9
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +000010#ifndef __IGEP00X0_H
11#define __IGEP00X0_H
12
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +010013#define CONFIG_NR_DRAM_BANKS 2
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +020014#define CONFIG_NAND
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040015
Enric Balletbò i Serrae37e9542013-12-06 21:30:24 +010016#include <configs/ti_omap3_common.h>
Enric Balletbo i Serraaa127df2013-02-07 00:40:05 +000017#include <asm/mach-types.h>
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040018
Tom Rinifa2f81b2016-08-26 13:30:43 -040019/*
20 * We are only ever GP parts and will utilize all of the "downloaded image"
21 * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB).
22 */
Enric Balletbo i Serrae7fbcbc2016-05-03 08:59:24 +020023#undef CONFIG_SPL_TEXT_BASE
Enric Balletbo i Serrae7fbcbc2016-05-03 08:59:24 +020024#define CONFIG_SPL_TEXT_BASE 0x40200000
25
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040026#define CONFIG_MISC_INIT_R
27
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040028#define CONFIG_REVISION_TAG 1
29
Enric Balletbo i Serra50bb94c2015-02-24 19:27:15 +010030/* Status LED available for IGEP0020 and IGEP0030 but not IGEP0032 */
Tom Rinid5324e22017-01-10 17:22:06 -050031#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) || \
32 (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
Enric Balletbo i Serraf3b4bc42015-01-28 15:01:32 +010033#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020)
34#define RED_LED_GPIO 27
Enric Balletbo i Serra50bb94c2015-02-24 19:27:15 +010035#elif (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030)
Enric Balletbo i Serraf3b4bc42015-01-28 15:01:32 +010036#define RED_LED_GPIO 16
37#endif
Enric Balletbo i Serra50bb94c2015-02-24 19:27:15 +010038#endif
Javier Martinez Canillas9d4f5422012-12-27 03:36:01 +000039
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040040/* USB */
Ladislav Michld636f2a2016-01-04 23:08:01 +010041#define CONFIG_USB_MUSB_UDC 1
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040042#define CONFIG_USB_OMAP3 1
43#define CONFIG_TWL4030_USB 1
44
45/* USB device configuration */
46#define CONFIG_USB_DEVICE 1
47#define CONFIG_USB_TTY 1
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040048
49/* Change these to suit your needs */
50#define CONFIG_USBD_VENDORID 0x0451
51#define CONFIG_USBD_PRODUCTID 0x5678
52#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
53#define CONFIG_USBD_PRODUCT_NAME "IGEP"
54
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +020055#define CONFIG_CMD_ONENAND
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040056
Enric Balletbò i Serra40372242015-09-07 08:28:09 +020057#ifndef CONFIG_SPL_BUILD
Enric Balletbo i Serra304a46c2011-04-19 09:16:36 -040058
Enric Balletbò i Serra40372242015-09-07 08:28:09 +020059/* Environment */
60#define ENV_DEVICE_SETTINGS \
61 "stdin=serial\0" \
62 "stdout=serial\0" \
63 "stderr=serial\0"
64
65#define MEM_LAYOUT_SETTINGS \
66 DEFAULT_LINUX_BOOT_ENV \
67 "scriptaddr=0x87E00000\0" \
68 "pxefile_addr_r=0x87F00000\0"
69
70#define BOOT_TARGET_DEVICES(func) \
71 func(MMC, mmc, 0)
72
73#include <config_distro_bootcmd.h>
74
Enric Balletbò i Serra40372242015-09-07 08:28:09 +020075#define CONFIG_EXTRA_ENV_SETTINGS \
76 ENV_DEVICE_SETTINGS \
77 MEM_LAYOUT_SETTINGS \
78 BOOTENV
79
80#endif
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040081
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040082/*
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040083 * SMSC911x Ethernet
84 */
85#if defined(CONFIG_CMD_NET)
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040086#define CONFIG_SMC911X
87#define CONFIG_SMC911X_32_BIT
Ladislav Michld636f2a2016-01-04 23:08:01 +010088#define CONFIG_SMC911X_BASE 0x2C000000
Enric Balletbo i Serra8a3f6bb2010-10-14 16:54:59 -040089#endif /* (CONFIG_CMD_NET) */
90
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +020091#define CONFIG_MTD_PARTITIONS
Ladislav Michla5debaa2016-07-12 20:28:33 +020092#define CONFIG_SYS_MTDPARTS_RUNTIME
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +020093
94/* OneNAND config */
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +020095#define CONFIG_USE_ONENAND_BOARD_INIT
96#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
97#define CONFIG_SYS_ONENAND_BLOCK_SIZE (128*1024)
Javier Martinez Canillasd271a612012-07-28 01:19:34 +000098
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +020099/* NAND config */
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +0200100#define CONFIG_SPL_OMAP3_ID_NAND
Stefano Babic55f1b392015-07-26 15:18:15 +0200101#define CONFIG_SYS_NAND_BUSWIDTH_16BIT
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000102#define CONFIG_SYS_NAND_5_ADDR_CYCLE
103#define CONFIG_SYS_NAND_PAGE_COUNT 64
104#define CONFIG_SYS_NAND_PAGE_SIZE 2048
105#define CONFIG_SYS_NAND_OOBSIZE 64
106#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
Ladislav Michl81fd8582015-10-12 18:09:14 +0200107#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
108#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
109 10, 11, 12, 13, 14, 15, 16, 17, \
110 18, 19, 20, 21, 22, 23, 24, 25, \
111 26, 27, 28, 29, 30, 31, 32, 33, \
112 34, 35, 36, 37, 38, 39, 40, 41, \
113 42, 43, 44, 45, 46, 47, 48, 49, \
114 50, 51, 52, 53, 54, 55, 56, 57, }
Javier Martinez Canillasd271a612012-07-28 01:19:34 +0000115#define CONFIG_SYS_NAND_ECCSIZE 512
Ladislav Michl81fd8582015-10-12 18:09:14 +0200116#define CONFIG_SYS_NAND_ECCBYTES 14
117#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
118#define CONFIG_NAND_OMAP_GPMC
119#define CONFIG_BCH
120
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +0200121/* UBI configuration */
122#define CONFIG_SPL_UBI 1
123#define CONFIG_SPL_UBI_MAX_VOL_LEBS 256
124#define CONFIG_SPL_UBI_MAX_PEB_SIZE (256*1024)
125#define CONFIG_SPL_UBI_MAX_PEBS 4096
126#define CONFIG_SPL_UBI_VOL_IDS 8
127#define CONFIG_SPL_UBI_LOAD_MONITOR_ID 0
128#define CONFIG_SPL_UBI_LOAD_KERNEL_ID 3
129#define CONFIG_SPL_UBI_LOAD_ARGS_ID 4
130#define CONFIG_SPL_UBI_PEB_OFFSET 4
131#define CONFIG_SPL_UBI_VID_OFFSET 512
132#define CONFIG_SPL_UBI_LEB_START 2048
133#define CONFIG_SPL_UBI_INFO_ADDR 0x88080000
134
135/* environment organization */
Ladislav Michl4b9dc7c2016-07-12 20:28:32 +0200136#define CONFIG_ENV_UBI_PART "UBI"
137#define CONFIG_ENV_UBI_VOLUME "config"
138#define CONFIG_ENV_UBI_VOLUME_REDUND "config_r"
139#define CONFIG_UBI_SILENCE_MSG 1
140#define CONFIG_UBIFS_SILENCE_MSG 1
141#define CONFIG_ENV_SIZE (32*1024)
142
Enric Balletbò i Serradc7a9e62012-03-05 11:32:16 +0000143#endif /* __IGEP00X0_H */