Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * J721E: SoC specific initialization |
| 4 | * |
| 5 | * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com/ |
| 6 | * Lokesh Vutla <lokeshvutla@ti.com> |
| 7 | */ |
| 8 | |
| 9 | #include <common.h> |
| 10 | #include <spl.h> |
| 11 | #include <asm/io.h> |
| 12 | #include <asm/armv7_mpu.h> |
Lokesh Vutla | 0a70492 | 2019-06-13 10:29:43 +0530 | [diff] [blame] | 13 | #include <asm/arch/hardware.h> |
Andreas Dannenberg | 9d1303b | 2019-06-13 10:29:47 +0530 | [diff] [blame] | 14 | #include <asm/arch/sysfw-loader.h> |
Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 15 | #include "common.h" |
Lokesh Vutla | 9c0ff86 | 2019-06-13 10:29:46 +0530 | [diff] [blame] | 16 | #include <asm/arch/sys_proto.h> |
| 17 | #include <linux/soc/ti/ti_sci_protocol.h> |
Andreas Dannenberg | 9d1303b | 2019-06-13 10:29:47 +0530 | [diff] [blame] | 18 | #include <dm.h> |
| 19 | #include <dm/uclass-internal.h> |
| 20 | #include <dm/pinctrl.h> |
Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 21 | |
| 22 | #ifdef CONFIG_SPL_BUILD |
Andreas Dannenberg | b73fcbc | 2019-06-13 10:29:44 +0530 | [diff] [blame] | 23 | static void mmr_unlock(u32 base, u32 partition) |
| 24 | { |
| 25 | /* Translate the base address */ |
| 26 | phys_addr_t part_base = base + partition * CTRL_MMR0_PARTITION_SIZE; |
| 27 | |
| 28 | /* Unlock the requested partition if locked using two-step sequence */ |
| 29 | writel(CTRLMMR_LOCK_KICK0_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK0); |
| 30 | writel(CTRLMMR_LOCK_KICK1_UNLOCK_VAL, part_base + CTRLMMR_LOCK_KICK1); |
| 31 | } |
| 32 | |
| 33 | static void ctrl_mmr_unlock(void) |
| 34 | { |
| 35 | /* Unlock all WKUP_CTRL_MMR0 module registers */ |
| 36 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 0); |
| 37 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 1); |
| 38 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 2); |
| 39 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 3); |
| 40 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 4); |
| 41 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 6); |
| 42 | mmr_unlock(WKUP_CTRL_MMR0_BASE, 7); |
| 43 | |
| 44 | /* Unlock all MCU_CTRL_MMR0 module registers */ |
| 45 | mmr_unlock(MCU_CTRL_MMR0_BASE, 0); |
| 46 | mmr_unlock(MCU_CTRL_MMR0_BASE, 1); |
| 47 | mmr_unlock(MCU_CTRL_MMR0_BASE, 2); |
| 48 | mmr_unlock(MCU_CTRL_MMR0_BASE, 3); |
| 49 | mmr_unlock(MCU_CTRL_MMR0_BASE, 4); |
| 50 | |
| 51 | /* Unlock all CTRL_MMR0 module registers */ |
| 52 | mmr_unlock(CTRL_MMR0_BASE, 0); |
| 53 | mmr_unlock(CTRL_MMR0_BASE, 1); |
| 54 | mmr_unlock(CTRL_MMR0_BASE, 2); |
| 55 | mmr_unlock(CTRL_MMR0_BASE, 3); |
| 56 | mmr_unlock(CTRL_MMR0_BASE, 4); |
| 57 | mmr_unlock(CTRL_MMR0_BASE, 5); |
| 58 | mmr_unlock(CTRL_MMR0_BASE, 6); |
| 59 | mmr_unlock(CTRL_MMR0_BASE, 7); |
| 60 | } |
| 61 | |
Andreas Dannenberg | f94a07c | 2019-06-13 10:29:45 +0530 | [diff] [blame] | 62 | /* |
| 63 | * This uninitialized global variable would normal end up in the .bss section, |
| 64 | * but the .bss is cleared between writing and reading this variable, so move |
| 65 | * it to the .data section. |
| 66 | */ |
| 67 | u32 bootindex __attribute__((section(".data"))); |
| 68 | |
| 69 | static void store_boot_index_from_rom(void) |
| 70 | { |
| 71 | bootindex = *(u32 *)(CONFIG_SYS_K3_BOOT_PARAM_TABLE_INDEX); |
| 72 | } |
| 73 | |
Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 74 | void board_init_f(ulong dummy) |
| 75 | { |
Andreas Dannenberg | 9d1303b | 2019-06-13 10:29:47 +0530 | [diff] [blame] | 76 | #if defined(CONFIG_K3_LOAD_SYSFW) |
| 77 | struct udevice *dev; |
| 78 | int ret; |
| 79 | #endif |
Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 80 | /* |
Andreas Dannenberg | f94a07c | 2019-06-13 10:29:45 +0530 | [diff] [blame] | 81 | * Cannot delay this further as there is a chance that |
| 82 | * K3_BOOT_PARAM_TABLE_INDEX can be over written by SPL MALLOC section. |
Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 83 | */ |
Andreas Dannenberg | f94a07c | 2019-06-13 10:29:45 +0530 | [diff] [blame] | 84 | store_boot_index_from_rom(); |
Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 85 | |
Andreas Dannenberg | b73fcbc | 2019-06-13 10:29:44 +0530 | [diff] [blame] | 86 | /* Make all control module registers accessible */ |
| 87 | ctrl_mmr_unlock(); |
| 88 | |
Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 89 | #ifdef CONFIG_CPU_V7R |
| 90 | setup_k3_mpu_regions(); |
| 91 | #endif |
| 92 | |
| 93 | /* Init DM early */ |
| 94 | spl_early_init(); |
| 95 | |
Andreas Dannenberg | 9d1303b | 2019-06-13 10:29:47 +0530 | [diff] [blame] | 96 | #ifdef CONFIG_K3_LOAD_SYSFW |
| 97 | /* |
| 98 | * Process pinctrl for the serial0 a.k.a. MCU_UART0 module and continue |
| 99 | * regardless of the result of pinctrl. Do this without probing the |
| 100 | * device, but instead by searching the device that would request the |
| 101 | * given sequence number if probed. The UART will be used by the system |
| 102 | * firmware (SYSFW) image for various purposes and SYSFW depends on us |
| 103 | * to initialize its pin settings. |
| 104 | */ |
| 105 | ret = uclass_find_device_by_seq(UCLASS_SERIAL, 0, true, &dev); |
| 106 | if (!ret) |
| 107 | pinctrl_select_state(dev, "default"); |
| 108 | |
| 109 | /* |
| 110 | * Load, start up, and configure system controller firmware. Provide |
| 111 | * the U-Boot console init function to the SYSFW post-PM configuration |
| 112 | * callback hook, effectively switching on (or over) the console |
| 113 | * output. |
| 114 | */ |
| 115 | k3_sysfw_loader(preloader_console_init); |
| 116 | #else |
Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 117 | /* Prepare console output */ |
| 118 | preloader_console_init(); |
Andreas Dannenberg | 9d1303b | 2019-06-13 10:29:47 +0530 | [diff] [blame] | 119 | #endif |
Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 120 | } |
Lokesh Vutla | 0a70492 | 2019-06-13 10:29:43 +0530 | [diff] [blame] | 121 | |
| 122 | u32 spl_boot_mode(const u32 boot_device) |
| 123 | { |
| 124 | switch (boot_device) { |
| 125 | case BOOT_DEVICE_MMC1: |
| 126 | return MMCSD_MODE_EMMCBOOT; |
| 127 | case BOOT_DEVICE_MMC2: |
| 128 | return MMCSD_MODE_FS; |
| 129 | default: |
| 130 | return MMCSD_MODE_RAW; |
| 131 | } |
| 132 | } |
| 133 | |
| 134 | static u32 __get_primary_bootmedia(u32 main_devstat, u32 wkup_devstat) |
| 135 | { |
| 136 | |
| 137 | u32 bootmode = (wkup_devstat & WKUP_DEVSTAT_PRIMARY_BOOTMODE_MASK) >> |
| 138 | WKUP_DEVSTAT_PRIMARY_BOOTMODE_SHIFT; |
| 139 | |
| 140 | bootmode |= (main_devstat & MAIN_DEVSTAT_BOOT_MODE_B_MASK) << |
| 141 | BOOT_MODE_B_SHIFT; |
| 142 | |
| 143 | if (bootmode == BOOT_DEVICE_OSPI || bootmode == BOOT_DEVICE_QSPI) |
| 144 | bootmode = BOOT_DEVICE_SPI; |
| 145 | |
| 146 | if (bootmode == BOOT_DEVICE_MMC2) { |
| 147 | u32 port = (main_devstat & |
| 148 | MAIN_DEVSTAT_PRIM_BOOTMODE_MMC_PORT_MASK) >> |
| 149 | MAIN_DEVSTAT_PRIM_BOOTMODE_PORT_SHIFT; |
| 150 | if (port == 0x0) |
| 151 | bootmode = BOOT_DEVICE_MMC1; |
| 152 | } |
| 153 | |
| 154 | return bootmode; |
| 155 | } |
| 156 | |
| 157 | u32 spl_boot_device(void) |
| 158 | { |
| 159 | u32 wkup_devstat = readl(CTRLMMR_WKUP_DEVSTAT); |
| 160 | u32 main_devstat; |
| 161 | |
| 162 | if (wkup_devstat & WKUP_DEVSTAT_MCU_OMLY_MASK) { |
| 163 | printf("ERROR: MCU only boot is not yet supported\n"); |
| 164 | return BOOT_DEVICE_RAM; |
| 165 | } |
| 166 | |
| 167 | /* MAIN CTRL MMR can only be read if MCU ONLY is 0 */ |
| 168 | main_devstat = readl(CTRLMMR_MAIN_DEVSTAT); |
| 169 | |
| 170 | /* ToDo: Add support for backup boot media */ |
| 171 | return __get_primary_bootmedia(main_devstat, wkup_devstat); |
| 172 | } |
Lokesh Vutla | c2562d7 | 2019-06-13 10:29:42 +0530 | [diff] [blame] | 173 | #endif |
Lokesh Vutla | 9c0ff86 | 2019-06-13 10:29:46 +0530 | [diff] [blame] | 174 | |
| 175 | #ifdef CONFIG_SYS_K3_SPL_ATF |
| 176 | |
| 177 | #define J721E_DEV_MCU_RTI0 262 |
| 178 | #define J721E_DEV_MCU_RTI1 263 |
| 179 | #define J721E_DEV_MCU_ARMSS0_CPU0 250 |
| 180 | #define J721E_DEV_MCU_ARMSS0_CPU1 251 |
| 181 | |
| 182 | void release_resources_for_core_shutdown(void) |
| 183 | { |
| 184 | struct ti_sci_handle *ti_sci; |
| 185 | struct ti_sci_dev_ops *dev_ops; |
| 186 | struct ti_sci_proc_ops *proc_ops; |
| 187 | int ret; |
| 188 | u32 i; |
| 189 | |
| 190 | const u32 put_device_ids[] = { |
| 191 | J721E_DEV_MCU_RTI0, |
| 192 | J721E_DEV_MCU_RTI1, |
| 193 | }; |
| 194 | |
| 195 | ti_sci = get_ti_sci_handle(); |
| 196 | dev_ops = &ti_sci->ops.dev_ops; |
| 197 | proc_ops = &ti_sci->ops.proc_ops; |
| 198 | |
| 199 | /* Iterate through list of devices to put (shutdown) */ |
| 200 | for (i = 0; i < ARRAY_SIZE(put_device_ids); i++) { |
| 201 | u32 id = put_device_ids[i]; |
| 202 | |
| 203 | ret = dev_ops->put_device(ti_sci, id); |
| 204 | if (ret) |
| 205 | panic("Failed to put device %u (%d)\n", id, ret); |
| 206 | } |
| 207 | |
| 208 | const u32 put_core_ids[] = { |
| 209 | J721E_DEV_MCU_ARMSS0_CPU1, |
| 210 | J721E_DEV_MCU_ARMSS0_CPU0, /* Handle CPU0 after CPU1 */ |
| 211 | }; |
| 212 | |
| 213 | /* Iterate through list of cores to put (shutdown) */ |
| 214 | for (i = 0; i < ARRAY_SIZE(put_core_ids); i++) { |
| 215 | u32 id = put_core_ids[i]; |
| 216 | |
| 217 | /* |
| 218 | * Queue up the core shutdown request. Note that this call |
| 219 | * needs to be followed up by an actual invocation of an WFE |
| 220 | * or WFI CPU instruction. |
| 221 | */ |
| 222 | ret = proc_ops->proc_shutdown_no_wait(ti_sci, id); |
| 223 | if (ret) |
| 224 | panic("Failed sending core %u shutdown message (%d)\n", |
| 225 | id, ret); |
| 226 | } |
| 227 | } |
| 228 | #endif |