blob: 72145e0aa3e0efd53b5b8b6e61d4be04522f1ef8 [file] [log] [blame]
wdenk429168e2004-08-02 23:39:03 +00001/***********************************************************************
2 *
3 * Copyright (C) 2004 by FS Forth-Systeme GmbH.
4 * All rights reserved.
5 *
6 * $Id: ns9750_eth.h,v 1.2 2004/02/24 13:25:39 mpietrek Exp $
7 * @Author: Markus Pietrek
8 * @References: [1] NS9750 Hardware Reference, December 2003
9 * [2] Intel LXT971 Datasheet #249414 Rev. 02
10 * [3] NS7520 Linux Ethernet Driver
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 *
27 ***********************************************************************/
28
29#ifndef __LXT971A_H__
30#define __LXT971A_H__
31
32/* PHY definitions (LXT971A) [2] */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020033#define PHY_LXT971_PORT_CFG (0x10)
34#define PHY_LXT971_STAT2 (0x11)
35#define PHY_LXT971_INT_ENABLE (0x12)
36#define PHY_LXT971_INT_STATUS (0x13)
37#define PHY_LXT971_LED_CFG (0x14)
38#define PHY_LXT971_DIG_CFG (0x1A)
39#define PHY_LXT971_TX_CTRL (0x1E)
wdenk429168e2004-08-02 23:39:03 +000040
wdenk429168e2004-08-02 23:39:03 +000041/* PORT_CFG Port Configuration Register Bit Fields */
42#define PHY_LXT971_PORT_CFG_RES1 (0x8000)
43#define PHY_LXT971_PORT_CFG_FORCE_LNK (0x4000)
44#define PHY_LXT971_PORT_CFG_TX_DISABLE (0x2000)
45#define PHY_LXT971_PORT_CFG_BYPASS_SCR (0x1000)
46#define PHY_LXT971_PORT_CFG_RES2 (0x0800)
47#define PHY_LXT971_PORT_CFG_JABBER (0x0400)
48#define PHY_LXT971_PORT_CFG_SQE (0x0200)
49#define PHY_LXT971_PORT_CFG_TP_LOOPBACK (0x0100)
50#define PHY_LXT971_PORT_CFG_CRS_SEL (0x0080)
51#define PHY_LXT971_PORT_CFG_SLEEP_MODE (0x0040)
52#define PHY_LXT971_PORT_CFG_PRE_EN (0x0020)
53#define PHY_LXT971_PORT_CFG_SLEEP_T_MA (0x0018)
54#define PHY_LXT971_PORT_CFG_SLEEP_T_104 (0x0010)
55#define PHY_LXT971_PORT_CFG_SLEEP_T_200 (0x0001)
56#define PHY_LXT971_PORT_CFG_SLEEP_T_304 (0x0000)
57#define PHY_LXT971_PORT_CFG_FLT_CODE_EN (0x0004)
58#define PHY_LXT971_PORT_CFG_ALT_NP (0x0002)
59#define PHY_LXT971_PORT_CFG_FIBER_SEL (0x0001)
60
61/* STAT2 Status Register #2 Bit Fields */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020062#define PHY_LXT971_STAT2_RES1 (0x8000)
63#define PHY_LXT971_STAT2_100BTX (0x4000)
wdenk429168e2004-08-02 23:39:03 +000064#define PHY_LXT971_STAT2_TX_STATUS (0x2000)
65#define PHY_LXT971_STAT2_RX_STATUS (0x1000)
66#define PHY_LXT971_STAT2_COL_STATUS (0x0800)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020067#define PHY_LXT971_STAT2_LINK (0x0400)
wdenk429168e2004-08-02 23:39:03 +000068#define PHY_LXT971_STAT2_DUPLEX_MODE (0x0200)
69#define PHY_LXT971_STAT2_AUTO_NEG (0x0100)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020070#define PHY_LXT971_STAT2_AUTO_NEG_COMP (0x0080)
71#define PHY_LXT971_STAT2_RES2 (0x0040)
wdenk429168e2004-08-02 23:39:03 +000072#define PHY_LXT971_STAT2_POLARITY (0x0020)
Wolfgang Denk53677ef2008-05-20 16:00:29 +020073#define PHY_LXT971_STAT2_PAUSE (0x0010)
74#define PHY_LXT971_STAT2_ERROR (0x0008)
75#define PHY_LXT971_STAT2_RES3 (0x0007)
wdenk429168e2004-08-02 23:39:03 +000076
77/* INT_ENABLE Interrupt Enable Register Bit Fields */
78#define PHY_LXT971_INT_ENABLE_RES1 (0xFF00)
79#define PHY_LXT971_INT_ENABLE_ANMSK (0x0080)
80#define PHY_LXT971_INT_ENABLE_SPEEDMSK (0x0040)
81#define PHY_LXT971_INT_ENABLE_DUPLEXMSK (0x0020)
82#define PHY_LXT971_INT_ENABLE_LINKMSK (0x0010)
83#define PHY_LXT971_INT_ENABLE_RES2 (0x000C)
84#define PHY_LXT971_INT_ENABLE_INTEN (0x0002)
85#define PHY_LXT971_INT_ENABLE_TINT (0x0001)
86
87/* INT_STATUS Interrupt Status Register Bit Fields */
88#define PHY_LXT971_INT_STATUS_RES1 (0xFF00)
89#define PHY_LXT971_INT_STATUS_ANDONE (0x0080)
90#define PHY_LXT971_INT_STATUS_SPEEDCHG (0x0040)
91#define PHY_LXT971_INT_STATUS_DUPLEXCHG (0x0020)
92#define PHY_LXT971_INT_STATUS_LINKCHG (0x0010)
93#define PHY_LXT971_INT_STATUS_RES2 (0x0008)
94#define PHY_LXT971_INT_STATUS_MDINT (0x0004)
95#define PHY_LXT971_INT_STATUS_RES3 (0x0003)
96
97/* LED_CFG Interrupt LED Configuration Register Bit Fields */
98#define PHY_LXT971_LED_CFG_SHIFT_LED1 (0x000C)
99#define PHY_LXT971_LED_CFG_SHIFT_LED2 (0x0008)
100#define PHY_LXT971_LED_CFG_SHIFT_LED3 (0x0004)
101#define PHY_LXT971_LED_CFG_LEDFREQ_MA (0x000C)
102#define PHY_LXT971_LED_CFG_LEDFREQ_RES (0x000C)
103#define PHY_LXT971_LED_CFG_LEDFREQ_100 (0x0008)
104#define PHY_LXT971_LED_CFG_LEDFREQ_60 (0x0004)
105#define PHY_LXT971_LED_CFG_LEDFREQ_30 (0x0000)
106#define PHY_LXT971_LED_CFG_PULSE_STR (0x0002)
107#define PHY_LXT971_LED_CFG_RES1 (0x0001)
108
109/* only one of these values must be shifted for each SHIFT_LED? */
110#define PHY_LXT971_LED_CFG_UNUSED1 (0x000F)
111#define PHY_LXT971_LED_CFG_DUPLEX_COL (0x000E)
112#define PHY_LXT971_LED_CFG_LINK_ACT (0x000D)
113#define PHY_LXT971_LED_CFG_LINK_RX (0x000C)
114#define PHY_LXT971_LED_CFG_TEST_BLK_SLW (0x000B)
115#define PHY_LXT971_LED_CFG_TEST_BLK_FST (0x000A)
116#define PHY_LXT971_LED_CFG_TEST_OFF (0x0009)
117#define PHY_LXT971_LED_CFG_TEST_ON (0x0008)
118#define PHY_LXT971_LED_CFG_RX_OR_TX (0x0007)
119#define PHY_LXT971_LED_CFG_UNUSED2 (0x0006)
120#define PHY_LXT971_LED_CFG_DUPLEX (0x0005)
121#define PHY_LXT971_LED_CFG_LINK (0x0004)
122#define PHY_LXT971_LED_CFG_COLLISION (0x0003)
123#define PHY_LXT971_LED_CFG_RECEIVE (0x0002)
124#define PHY_LXT971_LED_CFG_TRANSMIT (0x0001)
125#define PHY_LXT971_LED_CFG_SPEED (0x0000)
126
127/* DIG_CFG Digitial Configuration Register Bit Fields */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200128#define PHY_LXT971_DIG_CFG_RES1 (0xF000)
wdenk429168e2004-08-02 23:39:03 +0000129#define PHY_LXT971_DIG_CFG_MII_DRIVE (0x0800)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200130#define PHY_LXT971_DIG_CFG_RES2 (0x0400)
wdenk429168e2004-08-02 23:39:03 +0000131#define PHY_LXT971_DIG_CFG_SHOW_SYMBOL (0x0200)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200132#define PHY_LXT971_DIG_CFG_RES3 (0x01FF)
wdenk429168e2004-08-02 23:39:03 +0000133
134#define PHY_LXT971_MDIO_MAX_CLK (8000000)
135#define PHY_MDIO_MAX_CLK (2500000)
136
137/* TX_CTRL Transmit Control Register Bit Fields
138 documentation is buggy for this register, therefore setting not included */
139
140typedef enum
141{
142 PHY_NONE = 0x0000, /* no PHY detected yet */
143 PHY_LXT971A = 0x0013
144} PhyType;
145
146#endif /* __LXT971A_H__ */