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wdenkfe8c2802002-11-03 00:38:21 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * (C) Copyright 2001
6 * James F. Dougherty (jfd@cs.stanford.edu)
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27/*
28 *
29 * Configuration settings for the MOUSSE board.
30 * See also: http://www.vooha.com/
31 *
32 */
33
34/* ------------------------------------------------------------------------- */
35
36/*
37 * board/config.h - configuration options, board specific
38 */
39
40#ifndef __CONFIG_H
41#define __CONFIG_H
42
43/*
44 * High Level Configuration Options
45 * (easy to change)
46 */
47
48#define CONFIG_MPC824X 1
49#define CONFIG_MPC8240 1
50#define CONFIG_MOUSSE 1
51#define CFG_ADDR_MAP_B 1
52#define CONFIG_CONS_INDEX 1
53#define CONFIG_BAUDRATE 9600
54#if 1
55#define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */
56#else
57#define CONFIG_BOOTCOMMAND "bootm ffe10000"
58#endif
59#define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
60#define CONFIG_BOOTDELAY 3
Jon Loeliger8353e132007-07-08 14:14:17 -050061
62
63/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050064 * BOOTP options
65 */
66#define CONFIG_BOOTP_BOOTFILESIZE
67#define CONFIG_BOOTP_BOOTPATH
68#define CONFIG_BOOTP_GATEWAY
69#define CONFIG_BOOTP_HOSTNAME
70
71
72/*
Jon Loeliger8353e132007-07-08 14:14:17 -050073 * Command line configuration.
74 */
75#include <config_cmd_default.h>
76
77#define CONFIG_CMD_ASKENV
78#define CONFIG_CMD_DATE
79
80
wdenkfe8c2802002-11-03 00:38:21 +000081#define CONFIG_ENV_OVERWRITE 1
82#define CONFIG_ETH_ADDR "00:10:18:10:00:06"
83
84#define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */
Jon Loeliger8353e132007-07-08 14:14:17 -050085
wdenkfe8c2802002-11-03 00:38:21 +000086#include "../board/mousse/mousse.h"
87
88/*
89 * Miscellaneous configurable options
90 */
91#undef CFG_LONGHELP /* undef to save memory */
92#define CFG_PROMPT "=>" /* Monitor Command Prompt */
93#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
94#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
95#define CFG_MAXARGS 8 /* Max number of command args */
96
97#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
98#define CFG_LOAD_ADDR 0x00100000 /* Default load address */
99
100/*-----------------------------------------------------------------------
101 * Start addresses for the final memory configuration
102 * (Set up by the startup code)
103 * Please note that CFG_SDRAM_BASE _must_ start at 0
104 */
105#define CFG_SDRAM_BASE 0x00000000
106
107#ifdef DEBUG
108#define CFG_MONITOR_BASE CFG_SDRAM_BASE
109#else
110#define CFG_MONITOR_BASE CFG_FLASH_BASE
111#endif
112
113#ifdef DEBUG
114#define CFG_MONITOR_LEN (4 << 20) /* lots of mem ... */
115#else
116#define CFG_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */
117#endif
118#define CFG_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */
119
120#define CFG_MEMTEST_START 0x00004000 /* memtest works on */
121#define CFG_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
122
123
124#define CFG_EUMB_ADDR 0xFC000000
125
126#define CFG_ISA_MEM 0xFD000000
127#define CFG_ISA_IO 0xFE000000
128
129#define CFG_FLASH_BASE 0xFFF00000
130#define CFG_FLASH_SIZE ((uint)(512 * 1024))
131#define CFG_RESET_ADDRESS 0xFFF00100
132#define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/
133#define FLASH_BASE0_SIZE 0x80000 /* 512K */
134#define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB
135 1MB - 64K FLASH0 SEG =960K
136 (size=0xf0000)*/
137
138#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
139
140/*
141 * NS16550 Configuration
142 */
143#define CFG_NS16550
144#define CFG_NS16550_SERIAL
145
146#define CFG_NS16550_REG_SIZE 1
147
148#define CFG_NS16550_CLK 18432000
149
150#define CFG_NS16550_COM1 0xFFE08080
151
152/*-----------------------------------------------------------------------
153 * Definitions for initial stack pointer and data area (in DPRAM)
154 */
155#define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN
156#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
157#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
158#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
159#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
160
161/*
162 * Low Level Configuration Settings
163 * (address mappings, register initial values, etc.)
164 * You should know what you are doing if you make changes here.
165 * For the detail description refer to the MPC8240 user's manual.
166 */
167
168#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
169#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
170#define CFG_HZ 1000
171
172#define CFG_ETH_DEV_FN 0x00
173#define CFG_ETH_IOBASE 0x00104000
174
175
176 /* Bit-field values for MCCR1.
177 */
178#define CFG_ROMNAL 8
179#define CFG_ROMFAL 8
180
181 /* Bit-field values for MCCR2.
182 */
183#define CFG_REFINT 0xf5 /* Refresh interval */
184
185 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
186 */
187#define CFG_BSTOPRE 0x79
188
189#ifdef INCLUDE_ECC
190#define USE_ECC 1
191#else /* INCLUDE_ECC */
192#define USE_ECC 0
193#endif /* INCLUDE_ECC */
194
195
196 /* Bit-field values for MCCR3.
197 */
198#define CFG_REFREC 8 /* Refresh to activate interval */
199#define CFG_RDLAT (4+USE_ECC) /* Data latancy from read command */
200
201 /* Bit-field values for MCCR4.
202 */
203#define CFG_PRETOACT 3 /* Precharge to activate interval */
204#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
205#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
206#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
207#define CFG_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
208#define CFG_ACTORW 2
209#define CFG_REGISTERD_TYPE_BUFFER (1-USE_ECC)
210
211/* Memory bank settings.
212 * Only bits 20-29 are actually used from these vales to set the
213 * start/end addresses. The upper two bits will always be 0, and the lower
214 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
215 * address. Refer to the MPC8240 book.
216 */
217#define CFG_RAM_SIZE 0x04000000 /* 64MB */
218
219
220#define CFG_BANK0_START 0x00000000
221#define CFG_BANK0_END (CFG_RAM_SIZE - 1)
222#define CFG_BANK0_ENABLE 1
223#define CFG_BANK1_START 0x3ff00000
224#define CFG_BANK1_END 0x3fffffff
225#define CFG_BANK1_ENABLE 0
226#define CFG_BANK2_START 0x3ff00000
227#define CFG_BANK2_END 0x3fffffff
228#define CFG_BANK2_ENABLE 0
229#define CFG_BANK3_START 0x3ff00000
230#define CFG_BANK3_END 0x3fffffff
231#define CFG_BANK3_ENABLE 0
232#define CFG_BANK4_START 0x3ff00000
233#define CFG_BANK4_END 0x3fffffff
234#define CFG_BANK4_ENABLE 0
235#define CFG_BANK5_START 0x3ff00000
236#define CFG_BANK5_END 0x3fffffff
237#define CFG_BANK5_ENABLE 0
238#define CFG_BANK6_START 0x3ff00000
239#define CFG_BANK6_END 0x3fffffff
240#define CFG_BANK6_ENABLE 0
241#define CFG_BANK7_START 0x3ff00000
242#define CFG_BANK7_END 0x3fffffff
243#define CFG_BANK7_ENABLE 0
244
245#define CFG_ODCR 0x7f
246
247
248#define CFG_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory
wdenk8bde7f72003-06-27 21:31:46 +0000249 see 8240 book for details*/
wdenkfe8c2802002-11-03 00:38:21 +0000250#define PCI_MEM_SPACE1_START 0x80000000
251#define PCI_MEM_SPACE2_START 0xfd000000
252
253/* IBAT/DBAT Configuration */
254/* Ram: 64MB, starts at address-0, r/w instruction/data */
255#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
256#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
257#define CFG_DBAT0U CFG_IBAT0U
258#define CFG_DBAT0L CFG_IBAT0L
259
260/* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */
261#define CFG_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
262#if 0
263#define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\
264 BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
265#else
266#define CFG_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
267#endif
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200268#define CFG_DBAT1U CFG_IBAT1U
269#define CFG_DBAT1L CFG_IBAT1L
wdenkfe8c2802002-11-03 00:38:21 +0000270
271/* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200272#define CFG_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
273#define CFG_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
wdenkfe8c2802002-11-03 00:38:21 +0000274#define CFG_DBAT2U CFG_IBAT2U
275#define CFG_DBAT2L CFG_IBAT2L
276
277/* PCI Memory region 2: PCI Devices in 0xFD space */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200278#define CFG_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
279#define CFG_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
wdenkfe8c2802002-11-03 00:38:21 +0000280#define CFG_DBAT3U CFG_IBAT3U
281#define CFG_DBAT3L CFG_IBAT3L
282
283
284/*
285 * For booting Linux, the board info and command line data
286 * have to be in the first 8 MB of memory, since this is
287 * the maximum mapped by the Linux kernel during initialization.
288 */
289#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
290
291/*-----------------------------------------------------------------------
292 * FLASH organization
293 */
294#define CFG_MAX_FLASH_BANKS 3 /* Max number of flash banks */
295#define CFG_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
296
297#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
298#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
299
300#if 0
301#define CFG_ENV_IS_IN_FLASH 1
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200302#define CFG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */
wdenkfe8c2802002-11-03 00:38:21 +0000303#define CFG_ENV_SIZE 0x4000 /* Size of the Environment Sector */
304#else
305#define CFG_ENV_IS_IN_NVRAM 1
306#define CFG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
307#define CFG_ENV_OFFSET CFG_ENV_ADDR
308#define CFG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */
309#endif
310/*-----------------------------------------------------------------------
311 * Cache Configuration
312 */
313#define CFG_CACHELINE_SIZE 16
314
315
wdenkfe8c2802002-11-03 00:38:21 +0000316/*
317 * Internal Definitions
318 *
319 * Boot Flags
320 */
321#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
322#define BOOTFLAG_WARM 0x02 /* Software reboot */
323
324/* Localizations */
325#if 0
326#define CONFIG_ETHADDR 0:0:0:0:1:d
327#define CONFIG_IPADDR 172.16.40.113
328#define CONFIG_SERVERIP 172.16.40.111
329#else
330#define CONFIG_ETHADDR 0:0:0:0:1:d
331#define CONFIG_IPADDR 209.128.93.138
332#define CONFIG_SERVERIP 209.128.93.133
333#endif
334
335/*-----------------------------------------------------------------------
336 * PCI stuff
337 *-----------------------------------------------------------------------
338 */
339#define CONFIG_PCI /* include pci support */
340#undef CONFIG_PCI_PNP
341
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200342#define CONFIG_NET_MULTI /* Multi ethernet cards support */
wdenkfe8c2802002-11-03 00:38:21 +0000343
344#define CONFIG_TULIP
345
346#endif /* __CONFIG_H */