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wdenk73a8b272003-06-05 19:27:42 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2003-2005
wdenk73a8b272003-06-05 19:27:42 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31
32/*
33 * High Level Configuration Options
34 * (easy to change)
35 */
36
37#undef CONFIG_MPC860
38#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
39#define CONFIG_RPXLITE 1 /* RMU is the RPXlite clone */
40#define CONFIG_RMU 1
41
42#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
43#undef CONFIG_8xx_CONS_SMC2
44#undef CONFIG_8xx_CONS_NONE
45#define CONFIG_BAUDRATE 9600 /* console baudrate = 9600bps */
46#if 0
47#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
48#else
49#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
50#endif
51
wdenk73a8b272003-06-05 19:27:42 +000052#undef CONFIG_BOOTARGS
53#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020054 "bootp; " \
55 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
56 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenk73a8b272003-06-05 19:27:42 +000057 "bootm"
58
59#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
60#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
61
wdenkca75add2003-08-29 10:05:53 +000062/* enable I2C and select the hardware/software driver */
63#undef CONFIG_HARD_I2C /* I2C with hardware support */
64#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
65
66#define CFG_I2C_SPEED 40000 /* 40 kHz is supposed to work */
67#define CFG_I2C_SLAVE 0xFE
68
69/* Software (bit-bang) I2C driver configuration */
70#define PB_SCL 0x00000020 /* PB 26 */
71#define PB_SDA 0x00000010 /* PB 27 */
72
73#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
74#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
75#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
76#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
77#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
78 else immr->im_cpm.cp_pbdat &= ~PB_SDA
79#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
80 else immr->im_cpm.cp_pbdat &= ~PB_SCL
81#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
82
83/* M41T11 Serial Access Timekeeper(R) SRAM */
84#define CONFIG_RTC_M41T11 1
85#define CFG_I2C_RTC_ADDR 0x68
86#define CFG_M41T11_BASE_YEAR 1900 /* play along with the linux driver */
87
wdenk73a8b272003-06-05 19:27:42 +000088#undef CONFIG_WATCHDOG /* watchdog disabled */
89
Jon Loeliger90cc3eb2007-07-04 22:33:23 -050090
91/*
92 * Command line configuration.
93 */
94#include <config_cmd_default.h>
95
96#define CONFIG_CMD_DATE
97#define CONFIG_CMD_DHCP
98#define CONFIG_CMD_I2C
99#define CONFIG_CMD_NFS
100#define CONFIG_CMD_SNTP
101
wdenkca75add2003-08-29 10:05:53 +0000102
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500103/*
104 * BOOTP options
105 */
106#define CONFIG_BOOTP_SUBNETMASK
107#define CONFIG_BOOTP_GATEWAY
108#define CONFIG_BOOTP_HOSTNAME
109#define CONFIG_BOOTP_BOOTPATH
110#define CONFIG_BOOTP_BOOTFILESIZE
111
wdenk73a8b272003-06-05 19:27:42 +0000112
wdenkaf6d1df2003-12-03 23:53:42 +0000113#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
114#define CONFIG_AUTOBOOT_PROMPT "\nEnter password - autoboot in %d sec...\n"
115#define CONFIG_AUTOBOOT_DELAY_STR "system"
116
wdenk73a8b272003-06-05 19:27:42 +0000117/*
118 * Miscellaneous configurable options
119 */
120#define CFG_LONGHELP /* undef to save memory */
121#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500122#if defined(CONFIG_CMD_KGDB)
wdenk73a8b272003-06-05 19:27:42 +0000123#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
124#else
125#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
126#endif
127#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
128#define CFG_MAXARGS 16 /* max number of command args */
129#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
130
131#define CFG_MEMTEST_START 0x0040000 /* memtest works on */
132#define CFG_MEMTEST_END 0x00C0000 /* 4 ... 12 MB in DRAM */
133
134#define CFG_LOAD_ADDR 0x100000 /* default load address */
135
136#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
137
138#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
139
140/*
141 * Low Level Configuration Settings
142 * (address mappings, register initial values, etc.)
143 * You should know what you are doing if you make changes here.
144 */
145/*-----------------------------------------------------------------------
146 * Internal Memory Mapped Register
147 */
148#define CFG_IMMR 0xFA200000
149
150/*-----------------------------------------------------------------------
151 * Definitions for initial stack pointer and data area (in DPRAM)
152 */
153#define CFG_INIT_RAM_ADDR CFG_IMMR
154#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
155#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
156#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
157#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
158
159/*-----------------------------------------------------------------------
160 * Start addresses for the final memory configuration
161 * (Set up by the startup code)
162 * Please note that CFG_SDRAM_BASE _must_ start at 0
163 */
164#define CFG_SDRAM_BASE 0x00000000
wdenk7e780362004-04-08 22:31:29 +0000165#define CFG_FLASH_BASE (0-flash_info[0].size) /* Put flash at end */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500166#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
wdenk73a8b272003-06-05 19:27:42 +0000167#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
168#else
169#define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */
170#endif
wdenk7e780362004-04-08 22:31:29 +0000171#define CFG_MONITOR_BASE TEXT_BASE
wdenk73a8b272003-06-05 19:27:42 +0000172#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
173
174/*
175 * For booting Linux, the board info and command line data
176 * have to be in the first 8 MB of memory, since this is
177 * the maximum mapped by the Linux kernel during initialization.
178 */
179#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
180
181/*-----------------------------------------------------------------------
182 * FLASH organization
183 */
184#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
wdenk7e780362004-04-08 22:31:29 +0000185#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
wdenk73a8b272003-06-05 19:27:42 +0000186
187#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
188#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
189
190#define CFG_ENV_IS_IN_FLASH 1
wdenk7e780362004-04-08 22:31:29 +0000191#define CFG_ENV_ADDR ((TEXT_BASE) + 0x40000)
wdenk73a8b272003-06-05 19:27:42 +0000192#define CFG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
wdenk73a8b272003-06-05 19:27:42 +0000193
194/* Address and size of Redundant Environment Sector */
wdenk7e780362004-04-08 22:31:29 +0000195#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR+CFG_ENV_SIZE)
wdenk73a8b272003-06-05 19:27:42 +0000196#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
197
198/*-----------------------------------------------------------------------
wdenkca75add2003-08-29 10:05:53 +0000199 * Reset address
200 */
201#define CFG_RESET_ADDRESS ((ulong)((((immap_t *)CFG_IMMR)->im_clkrst.res)))
202
203/*-----------------------------------------------------------------------
wdenk73a8b272003-06-05 19:27:42 +0000204 * Cache Configuration
205 */
206#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger90cc3eb2007-07-04 22:33:23 -0500207#if defined(CONFIG_CMD_KGDB)
wdenk73a8b272003-06-05 19:27:42 +0000208#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
209#endif
210
211/*-----------------------------------------------------------------------
212 * SYPCR - System Protection Control 11-9
213 * SYPCR can only be written once after reset!
214 *-----------------------------------------------------------------------
215 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
216 */
217#if defined(CONFIG_WATCHDOG)
218#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
219 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
220#else
221#define CFG_SYPCR (SYPCR_SWTC | 0x00000600 | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
222#endif
223
224/*-----------------------------------------------------------------------
225 * SIUMCR - SIU Module Configuration 11-6
226 *-----------------------------------------------------------------------
227 * PCMCIA config., multi-function pin tri-state
228 */
229#define CFG_SIUMCR (SIUMCR_MLRC10)
230
231/*-----------------------------------------------------------------------
232 * TBSCR - Time Base Status and Control 11-26
233 *-----------------------------------------------------------------------
234 * Clear Reference Interrupt Status, Timebase freezing enabled
235 */
236#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF | TBSCR_TBE)
237
238/*-----------------------------------------------------------------------
239 * RTCSC - Real-Time Clock Status and Control Register 11-27
240 *-----------------------------------------------------------------------
241 */
242/*%%%#define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) */
243#define CFG_RTCSC (RTCSC_SEC | RTCSC_RTE)
244
245/*-----------------------------------------------------------------------
246 * PISCR - Periodic Interrupt Status and Control 11-31
247 *-----------------------------------------------------------------------
248 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
249 */
250#define CFG_PISCR (PISCR_PS | PISCR_PITF)
251
252/*-----------------------------------------------------------------------
253 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
254 *-----------------------------------------------------------------------
255 * Reset PLL lock status sticky bit, timer expired status bit and timer
256 * interrupt status bit
257 *
258 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
259 */
260/* up to 50 MHz we use a 1:1 clock */
261#define CFG_PLPRCR ( (5 << PLPRCR_MF_SHIFT) | PLPRCR_TEXPS )
262
263/*-----------------------------------------------------------------------
264 * SCCR - System Clock and reset Control Register 15-27
265 *-----------------------------------------------------------------------
266 * Set clock output, timebase and RTC source and divider,
267 * power management and some other internal clocks
268 */
269#define SCCR_MASK SCCR_EBDF00
270/* up to 50 MHz we use a 1:1 clock */
271#define CFG_SCCR (SCCR_COM00 | SCCR_TBS)
272
273/*-----------------------------------------------------------------------
274 * PCMCIA stuff
275 *-----------------------------------------------------------------------
276 *
277 */
278#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
279#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
280#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
281#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
282#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
283#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
284#define CFG_PCMCIA_IO_ADDR (0xEC000000)
285#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
286
287/*-----------------------------------------------------------------------
288 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
289 *-----------------------------------------------------------------------
290 */
291
292#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
293
294#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
295#undef CONFIG_IDE_LED /* LED for ide not supported */
296#undef CONFIG_IDE_RESET /* reset for ide not supported */
297
298#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
299#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
300
301#define CFG_ATA_IDE0_OFFSET 0x0000
302
303#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR
304
305/* Offset for data I/O */
306#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320)
307
308/* Offset for normal register accesses */
309#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
310
311/* Offset for alternate registers */
312#define CFG_ATA_ALT_OFFSET 0x0100
313
314/*-----------------------------------------------------------------------
315 *
316 *-----------------------------------------------------------------------
317 *
318 */
319/*#define CFG_DER 0x2002000F*/
320#define CFG_DER 0
321
322/*
323 * Init Memory Controller:
324 *
325 * BR0 and OR0 (FLASH)
326 */
327
wdenk7e780362004-04-08 22:31:29 +0000328#define FLASH_BASE_PRELIM 0xFC000000 /* FLASH base - up to 64 MB of flash */
329#define CFG_PRELIM_OR_AM 0xFC000000 /* OR addr mask - map 64 MB */
wdenk73a8b272003-06-05 19:27:42 +0000330
331/* FLASH timing: ACS = 0, TRLX = 0, CSNT = 0, SCY = 4, ETHR = 0, BIH = 1 */
332#define CFG_OR_TIMING_FLASH (OR_SCY_4_CLK | OR_BI)
333
334#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
335#define CFG_BR0_PRELIM ((FLASH_BASE_PRELIM & BR_BA_MSK) | BR_V)
336
337/*
338 * BR1 and OR1 (SDRAM)
339 *
340 */
341#define SDRAM_BASE_PRELIM 0x00000000 /* SDRAM base */
wdenkd94f92c2003-08-28 09:41:22 +0000342#define SDRAM_MAX_SIZE 0x08000000 /* max 128 MB */
wdenk73a8b272003-06-05 19:27:42 +0000343
344/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
345#define CFG_OR_TIMING_SDRAM 0x00000E00
346
wdenkd94f92c2003-08-28 09:41:22 +0000347#define CFG_OR1_PRELIM (0xF0000000 | CFG_OR_TIMING_SDRAM ) /* map 256 MB */
wdenk73a8b272003-06-05 19:27:42 +0000348#define CFG_BR1_PRELIM ((SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
349
350/* RPXLITE mem setting */
wdenk7e780362004-04-08 22:31:29 +0000351#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM & SRAM base */
352/* IMMR: 0xFA200000 IMMR base address - see above */
353#define CFG_BCSR_BASE 0xFA400000 /* BCSR base address */
354
355#define CFG_BR3_PRELIM (CFG_BCSR_BASE | BR_V) /* BCSR */
wdenk73a8b272003-06-05 19:27:42 +0000356#define CFG_OR3_PRELIM 0xFFFF8910
wdenk7e780362004-04-08 22:31:29 +0000357#define CFG_BR4_PRELIM (CFG_NVRAM_BASE | BR_PS_8 | BR_V) /* NVRAM & SRAM */
wdenk73a8b272003-06-05 19:27:42 +0000358#define CFG_OR4_PRELIM 0xFFFE0970
359
360/*
361 * Memory Periodic Timer Prescaler
362 */
363
364/* periodic timer for refresh */
365#define CFG_MAMR_PTA 20
366
367/*
368 * Refresh clock Prescalar
369 */
370#define CFG_MPTPR MPTPR_PTP_DIV2
371
372/*
373 * MAMR settings for SDRAM
374 */
375
wdenkd94f92c2003-08-28 09:41:22 +0000376/* 9 column SDRAM */
377#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk73a8b272003-06-05 19:27:42 +0000378 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
379 MAMR_RLFA_16X | MAMR_WLFA_16X | MAMR_TLFA_16X)
380
381/*
382 * Internal Definitions
383 *
384 * Boot Flags
385 */
386#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
387#define BOOTFLAG_WARM 0x02 /* Software reboot */
388
389/*
390 * BCSRx
391 *
392 * Board Status and Control Registers
393 *
394 */
395
wdenk7e780362004-04-08 22:31:29 +0000396#define BCSR0 (CFG_BCSR_BASE + 0)
397#define BCSR1 (CFG_BCSR_BASE + 1)
398#define BCSR2 (CFG_BCSR_BASE + 2)
399#define BCSR3 (CFG_BCSR_BASE + 3)
wdenk73a8b272003-06-05 19:27:42 +0000400
401#define BCSR0_ENMONXCVR 0x01 /* Monitor XVCR Control */
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200402#define BCSR0_ENNVRAM 0x02 /* CS4# Control */
wdenk73a8b272003-06-05 19:27:42 +0000403#define BCSR0_LED5 0x04 /* LED5 control 0='on' 1='off' */
404#define BCSR0_LED4 0x08 /* LED4 control 0='on' 1='off' */
405#define BCSR0_FULLDPLX 0x10 /* Ethernet XCVR Control */
406#define BCSR0_COLTEST 0x20
407#define BCSR0_ETHLPBK 0x40
408#define BCSR0_ETHEN 0x80
409
410#define BCSR1_PCVCTL7 0x01 /* PC Slot B Control */
411#define BCSR1_PCVCTL6 0x02
412#define BCSR1_PCVCTL5 0x04
413#define BCSR1_PCVCTL4 0x08
414#define BCSR1_IPB5SEL 0x10
415
416#define BCSR2_ENPA5HDR 0x08 /* USB Control */
417#define BCSR2_ENUSBCLK 0x10
418#define BCSR2_USBPWREN 0x20
419#define BCSR2_USBSPD 0x40
420#define BCSR2_USBSUSP 0x80
421
422#define BCSR3_BWRTC 0x01 /* Real Time Clock Battery */
423#define BCSR3_BWNVR 0x02 /* NVRAM Battery */
424#define BCSR3_RDY_BSY 0x04 /* Flash Operation */
425#define BCSR3_RPXL 0x08 /* Reserved (reads back '1') */
426#define BCSR3_D27 0x10 /* Dip Switch settings */
427#define BCSR3_D26 0x20
428#define BCSR3_D25 0x40
429#define BCSR3_D24 0x80
430
431#endif /* __CONFIG_H */