blob: 08cadf62715352eeaacf0fe54886c6abc734d38e [file] [log] [blame]
Wolfgang Denk32cb2c72006-07-21 11:31:42 +02001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 * Gary Jennejohn <gj@denx.de>
6 * David Mueller <d.mueller@elsoft.ch>
7 *
8 * Modified for the friendly-arm SBC-2410X by
9 * (C) Copyright 2005
10 * JinHua Luo, GuangDong Linux Center, <luo.jinhua@gd-linux.com>
11 *
12 * Configuation settings for the friendly-arm SBC-2410X board.
13 *
14 * See file CREDITS for list of people who contributed to this
15 * project.
16 *
17 * This program is free software; you can redistribute it and/or
18 * modify it under the terms of the GNU General Public License as
19 * published by the Free Software Foundation; either version 2 of
20 * the License, or (at your option) any later version.
21 *
22 * This program is distributed in the hope that it will be useful,
23 * but WITHOUT ANY WARRANTY; without even the implied warranty of
24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
25 * GNU General Public License for more details.
26 *
27 * You should have received a copy of the GNU General Public License
28 * along with this program; if not, write to the Free Software
29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
30 * MA 02111-1307 USA
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/*
37 * If we are developing, we might want to start armboot from ram
38 * so we MUST NOT initialize critical regs like mem-timing ...
39 */
40#undef CONFIG_SKIP_LOWLEVEL_INIT /* undef for developing */
41
42/*
43 * High Level Configuration Options
44 * (easy to change)
45 */
46#define CONFIG_ARM920T 1 /* This is an ARM920T Core */
47#define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */
48#define CONFIG_SBC2410X 1 /* on a friendly-arm SBC-2410X Board */
49
50/* input clock of PLL */
51#define CONFIG_SYS_CLK_FREQ 12000000/* the SBC2410X has 12MHz input clock */
52
53
54#define USE_920T_MMU 1
55#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
56
57/*
58 * Size of malloc() pool
59 */
60#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
61#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
62
63/*
64 * Hardware drivers
65 */
66#define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */
67#define CS8900_BASE 0x19000300
68#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */
69
70/*
71 * select serial console configuration
72 */
73#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SBC2410X */
74
75/************************************************************
76 * RTC
77 ************************************************************/
78#define CONFIG_RTC_S3C24X0 1
79
80/* allow to overwrite serial and ethaddr */
81#define CONFIG_ENV_OVERWRITE
82
83#define CONFIG_BAUDRATE 115200
84
Wolfgang Denk32cb2c72006-07-21 11:31:42 +020085
Jon Loeliger866e3082007-07-04 22:30:58 -050086/*
Jon Loeliger079a1362007-07-10 10:12:10 -050087 * BOOTP options
88 */
89#define CONFIG_BOOTP_BOOTFILESIZE
90#define CONFIG_BOOTP_BOOTPATH
91#define CONFIG_BOOTP_GATEWAY
92#define CONFIG_BOOTP_HOSTNAME
93
94
95/*
Jon Loeliger866e3082007-07-04 22:30:58 -050096 * Command line configuration.
97 */
98#include <config_cmd_default.h>
99
100#define CONFIG_CMD_ASKENV
101#define CONFIG_CMD_CACHE
102#define CONFIG_CMD_DATE
103#define CONFIG_CMD_DHCP
104#define CONFIG_CMD_ELF
105#define CONFIG_CMD_PING
Jon Loeliger866e3082007-07-04 22:30:58 -0500106
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200107
108#define CONFIG_BOOTDELAY 3
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200109#define CONFIG_BOOTARGS "console=ttySAC0 root=/dev/nfs " \
110 "nfsroot=192.168.0.1:/friendly-arm/rootfs_netserv " \
111 "ip=192.168.0.69:192.168.0.1:192.168.0.1:255.255.255.0:debian:eth0:off"
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200112#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
113#define CONFIG_NETMASK 255.255.255.0
114#define CONFIG_IPADDR 192.168.0.69
115#define CONFIG_SERVERIP 192.168.0.1
116/*#define CONFIG_BOOTFILE "elinos-lart" */
117#define CONFIG_BOOTCOMMAND "dhcp; bootm"
118
Jon Loeliger866e3082007-07-04 22:30:58 -0500119#if defined(CONFIG_CMD_KGDB)
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200120#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */
121/* what's this ? it's not used anywhere */
122#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */
123#endif
124
125/*
126 * Miscellaneous configurable options
127 */
128#define CFG_LONGHELP /* undef to save memory */
129#define CFG_PROMPT "[ ~ljh@GDLC ]# " /* Monitor Command Prompt */
130#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
131#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
132#define CFG_MAXARGS 16 /* max number of command args */
133#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
134
135#define CFG_MEMTEST_START 0x30000000 /* memtest works on */
136#define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */
137
138#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
139
140#define CFG_LOAD_ADDR 0x33000000 /* default load address */
141
142/* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */
143/* it to wrap 100 times (total 1562500) to get 1 sec. */
144#define CFG_HZ 1562500
145
146/* valid baudrates */
147#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
148
149/*-----------------------------------------------------------------------
150 * Stack sizes
151 *
152 * The stack sizes are set up in start.S using the settings below
153 */
154#define CONFIG_STACKSIZE (128*1024) /* regular stack */
155#ifdef CONFIG_USE_IRQ
156#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
157#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
158#endif
159
160/*-----------------------------------------------------------------------
161 * Physical Memory Map
162 */
163#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
164#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */
165#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
166
167#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
168
169#define CFG_FLASH_BASE PHYS_FLASH_1
170
171/*-----------------------------------------------------------------------
172 * FLASH and environment organization
173 */
174/* #define CONFIG_AMD_LV400 1 /\* uncomment this if you have a LV400 flash *\/ */
175
176#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */
177
178#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
179
180#ifdef CONFIG_AMD_LV800
181#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */
182#define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */
183#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */
184#endif
185
186#ifdef CONFIG_AMD_LV400
187#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */
188#define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */
189#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */
190#endif
191
192/* timeout values are in ticks */
193#define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */
194#define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */
195
196#define CFG_ENV_IS_IN_FLASH 1
197#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
198
199/*-----------------------------------------------------------------------
200 * NAND flash settings
201 */
Jon Loeliger866e3082007-07-04 22:30:58 -0500202#if defined(CONFIG_CMD_NAND)
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200203#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
204#define SECTORSIZE 512
205
206#define ADDR_COLUMN 1
207#define ADDR_PAGE 2
208#define ADDR_COLUMN_PAGE 3
209
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200210#define NAND_ChipID_UNKNOWN 0x00
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200211#define NAND_MAX_FLOORS 1
212#define NAND_MAX_CHIPS 1
213
214#define NAND_WAIT_READY(nand) NF_WaitRB()
215#define NAND_DISABLE_CE(nand) NF_SetCE(NFCE_HIGH)
216#define NAND_ENABLE_CE(nand) NF_SetCE(NFCE_LOW)
217#define WRITE_NAND_COMMAND(d, adr) NF_Cmd(d)
218#define WRITE_NAND_COMMANDW(d, adr) NF_CmdW(d)
219#define WRITE_NAND_ADDRESS(d, adr) NF_Addr(d)
220#define WRITE_NAND(d, adr) NF_Write(d)
221#define READ_NAND(adr) NF_Read()
222/* the following functions are NOP's because S3C24X0 handles this in hardware */
223#define NAND_CTL_CLRALE(nandptr)
224#define NAND_CTL_SETALE(nandptr)
225#define NAND_CTL_CLRCLE(nandptr)
226#define NAND_CTL_SETCLE(nandptr)
227/* #undef CONFIG_MTD_NAND_VERIFY_WRITE */
Jon Loeliger866e3082007-07-04 22:30:58 -0500228#endif /* CONFIG_CMD_NAND */
Wolfgang Denk32cb2c72006-07-21 11:31:42 +0200229
230#define CONFIG_SETUP_MEMORY_TAGS
231#define CONFIG_INITRD_TAG
232#define CONFIG_CMDLINE_TAG
233
234#define CFG_HUSH_PARSER
235#define CFG_PROMPT_HUSH_PS2 "> "
236
237#define CONFIG_CMDLINE_EDITING
238
239#ifdef CONFIG_CMDLINE_EDITING
240#undef CONFIG_AUTO_COMPLETE
241#else
242#define CONFIG_AUTO_COMPLETE
243#endif
244
245#endif /* __CONFIG_H */