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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Matt Waddelb80e41a2010-10-07 15:48:45 -06002/*
Ryan Harkincd4f46e2013-04-09 02:20:31 +00003 * (C) Copyright 2011 ARM Limited
Matt Waddelb80e41a2010-10-07 15:48:45 -06004 * (C) Copyright 2010 Linaro
5 * Matt Waddel, <matt.waddel@linaro.org>
6 *
7 * Configuration for Versatile Express. Parts were derived from other ARM
8 * configurations.
Matt Waddelb80e41a2010-10-07 15:48:45 -06009 */
10
Ryan Harkincd4f46e2013-04-09 02:20:31 +000011#ifndef __VEXPRESS_COMMON_H
12#define __VEXPRESS_COMMON_H
13
14/*
15 * Definitions copied from linux kernel:
16 * arch/arm/mach-vexpress/include/mach/motherboard.h
17 */
18#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
19/* CS register bases for the original memory map. */
20#define V2M_PA_CS0 0x40000000
21#define V2M_PA_CS1 0x44000000
22#define V2M_PA_CS2 0x48000000
23#define V2M_PA_CS3 0x4c000000
24#define V2M_PA_CS7 0x10000000
25
26#define V2M_PERIPH_OFFSET(x) (x << 12)
27#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(0))
28#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
29#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
30
31#define V2M_BASE 0x60000000
Ryan Harkincd4f46e2013-04-09 02:20:31 +000032#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
33/* CS register bases for the extended memory map. */
34#define V2M_PA_CS0 0x08000000
35#define V2M_PA_CS1 0x0c000000
36#define V2M_PA_CS2 0x14000000
37#define V2M_PA_CS3 0x18000000
38#define V2M_PA_CS7 0x1c000000
39
40#define V2M_PERIPH_OFFSET(x) (x << 16)
41#define V2M_SYSREGS (V2M_PA_CS7 + V2M_PERIPH_OFFSET(1))
42#define V2M_SYSCTL (V2M_PA_CS7 + V2M_PERIPH_OFFSET(2))
43#define V2M_SERIAL_BUS_PCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(3))
44
45#define V2M_BASE 0x80000000
Ryan Harkincd4f46e2013-04-09 02:20:31 +000046#endif
47
48/*
49 * Physical addresses, offset from V2M_PA_CS0-3
50 */
51#define V2M_NOR0 (V2M_PA_CS0)
52#define V2M_NOR1 (V2M_PA_CS1)
53#define V2M_SRAM (V2M_PA_CS2)
54#define V2M_VIDEO_SRAM (V2M_PA_CS3 + 0x00000000)
Ryan Harkincd4f46e2013-04-09 02:20:31 +000055#define V2M_ISP1761 (V2M_PA_CS3 + 0x03000000)
56
57/* Common peripherals relative to CS7. */
58#define V2M_AACI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(4))
59#define V2M_MMCI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(5))
60#define V2M_KMI0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(6))
61#define V2M_KMI1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(7))
62
63#define V2M_UART0 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(9))
64#define V2M_UART1 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(10))
65#define V2M_UART2 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(11))
66#define V2M_UART3 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(12))
67
68#define V2M_WDT (V2M_PA_CS7 + V2M_PERIPH_OFFSET(15))
69
70#define V2M_TIMER01 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(17))
71#define V2M_TIMER23 (V2M_PA_CS7 + V2M_PERIPH_OFFSET(18))
72
73#define V2M_SERIAL_BUS_DVI (V2M_PA_CS7 + V2M_PERIPH_OFFSET(22))
74#define V2M_RTC (V2M_PA_CS7 + V2M_PERIPH_OFFSET(23))
75
76#define V2M_CF (V2M_PA_CS7 + V2M_PERIPH_OFFSET(26))
77
78#define V2M_CLCD (V2M_PA_CS7 + V2M_PERIPH_OFFSET(31))
79#define V2M_SIZE_CS7 V2M_PERIPH_OFFSET(32)
80
81/* System register offsets. */
82#define V2M_SYS_CFGDATA (V2M_SYSREGS + 0x0a0)
83#define V2M_SYS_CFGCTRL (V2M_SYSREGS + 0x0a4)
84#define V2M_SYS_CFGSTAT (V2M_SYSREGS + 0x0a8)
85
86/*
87 * Configuration
88 */
89#define SYS_CFG_START (1 << 31)
90#define SYS_CFG_WRITE (1 << 30)
91#define SYS_CFG_OSC (1 << 20)
92#define SYS_CFG_VOLT (2 << 20)
93#define SYS_CFG_AMP (3 << 20)
94#define SYS_CFG_TEMP (4 << 20)
95#define SYS_CFG_RESET (5 << 20)
96#define SYS_CFG_SCC (6 << 20)
97#define SYS_CFG_MUXFPGA (7 << 20)
98#define SYS_CFG_SHUTDOWN (8 << 20)
99#define SYS_CFG_REBOOT (9 << 20)
100#define SYS_CFG_DVIMODE (11 << 20)
101#define SYS_CFG_POWER (12 << 20)
102#define SYS_CFG_SITE_MB (0 << 16)
103#define SYS_CFG_SITE_DB1 (1 << 16)
104#define SYS_CFG_SITE_DB2 (2 << 16)
105#define SYS_CFG_STACK(n) ((n) << 12)
106
107#define SYS_CFG_ERR (1 << 1)
108#define SYS_CFG_COMPLETE (1 << 0)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600109
110/* Board info register */
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000111#define SYS_ID V2M_SYSREGS
Matt Waddelb80e41a2010-10-07 15:48:45 -0600112#define CONFIG_REVISION_TAG 1
113
Matt Waddelb80e41a2010-10-07 15:48:45 -0600114#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
115#define CONFIG_SETUP_MEMORY_TAGS 1
Aneesh Ve47f2db2011-06-16 23:30:48 +0000116#define CONFIG_SYS_L2CACHE_OFF 1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600117#define CONFIG_INITRD_TAG 1
Grant Likely2fa8ca92011-03-28 09:59:07 +0000118
Matt Waddelb80e41a2010-10-07 15:48:45 -0600119/* Size of malloc() pool */
Otavio Salvador58fcca02018-11-20 16:47:12 -0200120#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024) /* >= 512 KiB */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600121
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000122#define SCTL_BASE V2M_SYSCTL
Matt Waddelb80e41a2010-10-07 15:48:45 -0600123#define VEXPRESS_FLASHPROG_FLVPPEN (1 << 0)
124
Rob Herringb3a7f222013-10-04 10:22:45 -0500125#define CONFIG_SYS_TIMER_RATE 1000000
Ian Campbellcb7ee1b2013-11-17 15:17:42 +0000126#define CONFIG_SYS_TIMER_COUNTER (V2M_TIMER01 + 0x4)
Rob Herringb3a7f222013-10-04 10:22:45 -0500127#define CONFIG_SYS_TIMER_COUNTS_DOWN
128
Matt Waddelb80e41a2010-10-07 15:48:45 -0600129/* PL011 Serial Configuration */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600130#define CONFIG_PL011_CLOCK 24000000
131#define CONFIG_PL01x_PORTS {(void *)CONFIG_SYS_SERIAL0, \
132 (void *)CONFIG_SYS_SERIAL1}
Matt Waddelb80e41a2010-10-07 15:48:45 -0600133
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000134#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
135#define CONFIG_SYS_SERIAL0 V2M_UART0
136#define CONFIG_SYS_SERIAL1 V2M_UART1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600137
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000138#define CONFIG_ARM_PL180_MMCI_BASE V2M_MMCI
Matt Waddelf0c64522011-04-16 11:54:08 +0000139#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127
140#define CONFIG_ARM_PL180_MMCI_CLOCK_FREQ 6250000
Matt Waddelb80e41a2010-10-07 15:48:45 -0600141
142/* BOOTP options */
143#define CONFIG_BOOTP_BOOTFILESIZE
Matt Waddelb80e41a2010-10-07 15:48:45 -0600144
145/* Miscellaneous configurable options */
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000146#define CONFIG_SYS_LOAD_ADDR (V2M_BASE + 0x8000)
147#define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600148
Matt Waddelb80e41a2010-10-07 15:48:45 -0600149/* Physical Memory Map */
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000150#define PHYS_SDRAM_1 (V2M_BASE) /* SDRAM Bank #1 */
151#define PHYS_SDRAM_2 (((unsigned int)V2M_BASE) + \
152 ((unsigned int)0x20000000))
Matt Waddelb80e41a2010-10-07 15:48:45 -0600153#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512 MB */
154#define PHYS_SDRAM_2_SIZE 0x20000000 /* 512 MB */
155
156/* additions for new relocation code */
157#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk553f0982010-10-26 13:32:32 +0200158#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Matt Waddelb80e41a2010-10-07 15:48:45 -0600159#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_SDRAM_BASE + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200160 CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200161 GENERATED_GBL_DATA_SIZE)
Matt Waddelb80e41a2010-10-07 15:48:45 -0600162#define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_GBL_DATA_OFFSET
Dennis Gilmoreacb5ff02015-06-28 14:05:12 -0500163
Matt Waddelb80e41a2010-10-07 15:48:45 -0600164/* Basic environment settings */
Dennis Gilmoreacb5ff02015-06-28 14:05:12 -0500165#define BOOT_TARGET_DEVICES(func) \
166 func(MMC, mmc, 1) \
167 func(MMC, mmc, 0) \
168 func(PXE, pxe, na) \
169 func(DHCP, dhcp, na)
170#include <config_distro_bootcmd.h>
171
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000172#ifdef CONFIG_VEXPRESS_ORIGINAL_MEMORY_MAP
173#define CONFIG_PLATFORM_ENV_SETTINGS \
Matt Waddelb80e41a2010-10-07 15:48:45 -0600174 "loadaddr=0x80008000\0" \
Jason Hobbs75e7f3f2011-08-23 11:06:59 +0000175 "ramdisk_addr_r=0x61000000\0" \
176 "kernel_addr=0x44100000\0" \
177 "ramdisk_addr=0x44800000\0" \
178 "maxramdisk=0x1800000\0" \
Jason Hobbse21669f2011-08-23 11:07:00 +0000179 "pxefile_addr_r=0x88000000\0" \
Dennis Gilmoreacb5ff02015-06-28 14:05:12 -0500180 "scriptaddr=0x88000000\0" \
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000181 "kernel_addr_r=0x80008000\0"
182#elif defined(CONFIG_VEXPRESS_EXTENDED_MEMORY_MAP)
183#define CONFIG_PLATFORM_ENV_SETTINGS \
184 "loadaddr=0xa0008000\0" \
185 "ramdisk_addr_r=0x81000000\0" \
186 "kernel_addr=0x0c100000\0" \
187 "ramdisk_addr=0x0c800000\0" \
188 "maxramdisk=0x1800000\0" \
189 "pxefile_addr_r=0xa8000000\0" \
Dennis Gilmoreacb5ff02015-06-28 14:05:12 -0500190 "scriptaddr=0xa8000000\0" \
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000191 "kernel_addr_r=0xa0008000\0"
192#endif
193#define CONFIG_EXTRA_ENV_SETTINGS \
194 CONFIG_PLATFORM_ENV_SETTINGS \
Dennis Gilmoreacb5ff02015-06-28 14:05:12 -0500195 BOOTENV \
Matt Waddelb80e41a2010-10-07 15:48:45 -0600196 "console=ttyAMA0,38400n8\0" \
197 "dram=1024M\0" \
198 "root=/dev/sda1 rw\0" \
199 "mtd=armflash:1M@0x800000(uboot),7M@0x1000000(kernel)," \
200 "24M@0x2000000(initrd)\0" \
201 "flashargs=setenv bootargs root=${root} console=${console} " \
202 "mem=${dram} mtdparts=${mtd} mmci.fmax=190000 " \
203 "devtmpfs.mount=0 vmalloc=256M\0" \
204 "bootflash=run flashargs; " \
Jason Hobbs75e7f3f2011-08-23 11:06:59 +0000205 "cp ${ramdisk_addr} ${ramdisk_addr_r} ${maxramdisk}; " \
Kristian Amlied4babee2020-02-25 18:22:16 +0100206 "bootm ${kernel_addr} ${ramdisk_addr_r}\0" \
207 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0"
Matt Waddelb80e41a2010-10-07 15:48:45 -0600208
209/* FLASH and environment organization */
210#define PHYS_FLASH_SIZE 0x04000000 /* 64MB */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600211#define CONFIG_SYS_FLASH_SIZE 0x04000000
212#define CONFIG_SYS_MAX_FLASH_BANKS 2
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000213#define CONFIG_SYS_FLASH_BASE0 V2M_NOR0
214#define CONFIG_SYS_FLASH_BASE1 V2M_NOR1
Matt Waddelb80e41a2010-10-07 15:48:45 -0600215#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE0
216
217/* Timeout values in ticks */
218#define CONFIG_SYS_FLASH_ERASE_TOUT (2 * CONFIG_SYS_HZ) /* Erase Timeout */
219#define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Write Timeout */
220
221/* 255 0x40000 sectors + first or last sector may have 4 erase regions = 259 */
222#define CONFIG_SYS_MAX_FLASH_SECT 259 /* Max sectors */
223#define FLASH_MAX_SECTOR_SIZE 0x00040000 /* 256 KB sectors */
224
225/* Room required on the stack for the environment data */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600226
Matt Waddelb80e41a2010-10-07 15:48:45 -0600227/*
228 * Amount of flash used for environment:
229 * We don't know which end has the small erase blocks so we use the penultimate
230 * sector location for the environment
231 */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600232
233/* Store environment at top of flash */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600234#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
235#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE0, \
236 CONFIG_SYS_FLASH_BASE1 }
237
238/* Monitor Command Prompt */
239#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
Matt Waddelb80e41a2010-10-07 15:48:45 -0600240
Ryan Harkincd4f46e2013-04-09 02:20:31 +0000241#endif /* VEXPRESS_COMMON_H */