blob: c74973edec1ee3dd752ce3a4f6a91ac3920febe7 [file] [log] [blame]
Troy Kisky71a988a2013-01-18 16:14:24 +00001/*
2 * (C) Copyright 2009
3 * Stefano Babic DENX Software Engineering sbabic@denx.de.
4 *
5 * (C) Copyright 2010
6 * Klaus Steinhammer TTECH Control Gmbh kst@tttech.com
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
Troy Kisky71a988a2013-01-18 16:14:24 +00009 *
Anatolij Gustschinb1e6c4c2013-04-30 11:15:33 +000010 * Refer doc/README.imximage for more details about how-to configure
Troy Kisky71a988a2013-01-18 16:14:24 +000011 * and create imximage boot image
12 *
13 * The syntax is taken as close as possible with the kwbimage
14 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020015
Troy Kisky71a988a2013-01-18 16:14:24 +000016/*
17 * Boot Device : one of
18 * spi, nand, onenand, sd
19 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020020BOOT_FROM spi
21
Troy Kisky71a988a2013-01-18 16:14:24 +000022/*
23 * Device Configuration Data (DCD)
24 *
25 * Each entry must have the format:
26 * Addr-type Address Value
27 *
28 * where:
29 * Addr-type register length (1,2 or 4 bytes)
30 * Address absolute address of the register
31 * value value to be stored in the register
32 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020033
Troy Kisky71a988a2013-01-18 16:14:24 +000034/*
35 * #######################
36 * ### Disable WDOG ###
37 * #######################
38 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020039DATA 2 0x73f98000 0x30
40
Troy Kisky71a988a2013-01-18 16:14:24 +000041/*
42 * #######################
43 * ### SET DDR Clk ###
44 * #######################
45 */
46/* CCM: CBMCR - ddr_clk_sel: axi_b (133MHz) */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020047DATA 4 0x73FD4018 0x000024C0
48
Troy Kisky71a988a2013-01-18 16:14:24 +000049/* DOUBLE SPI CLK (13MHz->26 MHz Clock) */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020050DATA 4 0x73FD4038 0x2010241
51
Troy Kisky71a988a2013-01-18 16:14:24 +000052/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MOSI HYS_ENABLE | DRV_MAX | SRE_FAST */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020053DATA 4 0x73fa8600 0x00000107
Troy Kisky71a988a2013-01-18 16:14:24 +000054/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_MISO HYS_ENABLE | DRV_MAX | SRE_FAST */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020055DATA 4 0x73fa8604 0x00000107
Troy Kisky71a988a2013-01-18 16:14:24 +000056/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS0 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020057DATA 4 0x73fa8608 0x00000187
Troy Kisky71a988a2013-01-18 16:14:24 +000058/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SS1 HYS_ENABLE | PKE_ENABLE | DRV_MAX | SRE_FAST */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020059DATA 4 0x73fa860c 0x00000187
Troy Kisky71a988a2013-01-18 16:14:24 +000060/* IOMUXC_SW_PAD_CTL_PAD_CSPI1_SCLK HYS_ENABLE | DRV_MAX | SRE_FAST */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020061DATA 4 0x73fa8614 0x00000107
Troy Kisky71a988a2013-01-18 16:14:24 +000062/* IOMUXC_SW_PAD_CTL_PAD_DI1_PIN11 HYS_ENABLE | DRV_MAX | SRE_FAST (CSPI1_SS2) */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020063DATA 4 0x73fa86a8 0x00000187
64
Troy Kisky71a988a2013-01-18 16:14:24 +000065/*
66 * #######################
67 * ### Settings IOMUXC ###
68 * #######################
69 */
70/*
71 * DDR IOMUX configuration
72 * Control, Data, Address pads are in their default state: HIGH DS, FAST SR.
73 * IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK MAX DS
74 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020075DATA 4 0x73fa84b8 0x000000e7
Troy Kisky71a988a2013-01-18 16:14:24 +000076/* PVTC MAX (at GPC, PGR reg) */
77/* DATA 4 0x73FD8004 0x1fc00000 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020078
Troy Kisky71a988a2013-01-18 16:14:24 +000079/* DQM0 DS high slew rate slow */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020080DATA 4 0x73fa84d4 0x000000e4
Troy Kisky71a988a2013-01-18 16:14:24 +000081/* DQM1 DS high slew rate slow */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020082DATA 4 0x73fa84d8 0x000000e4
Troy Kisky71a988a2013-01-18 16:14:24 +000083/* DQM2 DS high slew rate slow */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020084DATA 4 0x73fa84dc 0x000000e4
Troy Kisky71a988a2013-01-18 16:14:24 +000085/* DQM3 DS high slew rate slow */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020086DATA 4 0x73fa84e0 0x000000e4
87
Troy Kisky71a988a2013-01-18 16:14:24 +000088/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0 DS high & SLEW slow */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020089DATA 4 0x73fa84bc 0x000000c4
Troy Kisky71a988a2013-01-18 16:14:24 +000090/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1 DS high & SLEW slow */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020091DATA 4 0x73fa84c0 0x000000c4
Troy Kisky71a988a2013-01-18 16:14:24 +000092/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2 DS high & SLEW slow */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020093DATA 4 0x73fa84c4 0x000000c4
Troy Kisky71a988a2013-01-18 16:14:24 +000094/* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3 DS high & SLEW slow */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020095DATA 4 0x73fa84c8 0x000000c4
96
Troy Kisky71a988a2013-01-18 16:14:24 +000097/* DRAM_DATA B0 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +020098DATA 4 0x73fa88a4 0x00000004
Troy Kisky71a988a2013-01-18 16:14:24 +000099/* DRAM_DATA B1 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200100DATA 4 0x73fa88ac 0x00000004
Troy Kisky71a988a2013-01-18 16:14:24 +0000101/* DRAM_DATA B2 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200102DATA 4 0x73fa88b8 0x00000004
Troy Kisky71a988a2013-01-18 16:14:24 +0000103/* DRAM_DATA B3 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200104DATA 4 0x73fa882c 0x00000004
105
Troy Kisky71a988a2013-01-18 16:14:24 +0000106/* DRAM_DATA B0 slew rate */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200107DATA 4 0x73fa8878 0x00000000
Troy Kisky71a988a2013-01-18 16:14:24 +0000108/* DRAM_DATA B1 slew rate */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200109DATA 4 0x73fa8880 0x00000000
Troy Kisky71a988a2013-01-18 16:14:24 +0000110/* DRAM_DATA B2 slew rate */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200111DATA 4 0x73fa888c 0x00000000
Troy Kisky71a988a2013-01-18 16:14:24 +0000112/* DRAM_DATA B3 slew rate */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200113DATA 4 0x73fa889c 0x00000000
114
Troy Kisky71a988a2013-01-18 16:14:24 +0000115/*
116 * #######################
117 * ### Configure SDRAM ###
118 * #######################
119 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200120
Troy Kisky71a988a2013-01-18 16:14:24 +0000121/* Configure CS0 */
122/* ####################### */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200123
Troy Kisky71a988a2013-01-18 16:14:24 +0000124/* ESDCTL0: Enable controller */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200125DATA 4 0x83fd9000 0x83220000
126
Jeroen Hofsteec84f9e02014-06-10 23:16:09 +0200127/* Init DRAM on CS0 */
Troy Kisky71a988a2013-01-18 16:14:24 +0000128/* ESDSCR: Precharge command */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200129DATA 4 0x83fd9014 0x04008008
Troy Kisky71a988a2013-01-18 16:14:24 +0000130/* ESDSCR: Refresh command */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200131DATA 4 0x83fd9014 0x00008010
Troy Kisky71a988a2013-01-18 16:14:24 +0000132/* ESDSCR: Refresh command */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200133DATA 4 0x83fd9014 0x00008010
Troy Kisky71a988a2013-01-18 16:14:24 +0000134/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200135DATA 4 0x83fd9014 0x00338018
Troy Kisky71a988a2013-01-18 16:14:24 +0000136/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200137DATA 4 0x83fd9014 0x0020801a
Troy Kisky71a988a2013-01-18 16:14:24 +0000138/* ESDSCR */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200139DATA 4 0x83fd9014 0x00008000
140
Troy Kisky71a988a2013-01-18 16:14:24 +0000141/* ESDSCR: EMR with full Drive strength */
142/* DATA 4 0x83fd9014 0x0000801a */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200143
Troy Kisky71a988a2013-01-18 16:14:24 +0000144/* ESDCTL0: 14 ROW, 10 COL, 32Bit, SREF=8 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200145DATA 4 0x83fd9000 0xC3220000
146
Troy Kisky71a988a2013-01-18 16:14:24 +0000147/*
148 * ESDCFG0: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
149 * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
150 * DATA 4 0x83fd9004 0xC33574AA
151 */
152/*
153 * micron mDDR
154 * ESDCFG0: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
155 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
156 * DATA 4 0x83FD9004 0x101564a8
157 */
158/*
159 * hynix mDDR
160 * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
161 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
162 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200163DATA 4 0x83FD9004 0x704564a8
164
Troy Kisky71a988a2013-01-18 16:14:24 +0000165/* ESDMISC: AP=10, Bank interleaving on, MIF3 en, RALAT=2 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200166DATA 4 0x83fd9010 0x000a1700
167
Troy Kisky71a988a2013-01-18 16:14:24 +0000168/* Configure CS1 */
169/* ####################### */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200170
Troy Kisky71a988a2013-01-18 16:14:24 +0000171/* ESDCTL1: Enable controller */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200172DATA 4 0x83fd9008 0x83220000
173
Troy Kisky71a988a2013-01-18 16:14:24 +0000174/* Init DRAM on CS1 */
175/* ESDSCR: Precharge command */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200176DATA 4 0x83fd9014 0x0400800c
Troy Kisky71a988a2013-01-18 16:14:24 +0000177/* ESDSCR: Refresh command */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200178DATA 4 0x83fd9014 0x00008014
Troy Kisky71a988a2013-01-18 16:14:24 +0000179/* ESDSCR: Refresh command */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200180DATA 4 0x83fd9014 0x00008014
Troy Kisky71a988a2013-01-18 16:14:24 +0000181/* ESDSCR: LMR with CAS=3 and BL=3 (Burst Length = 8) */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200182DATA 4 0x83fd9014 0x0033801c
Troy Kisky71a988a2013-01-18 16:14:24 +0000183/* ESDSCR: EMR with half Drive strength (= medium strength @ i.MX51) */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200184DATA 4 0x83fd9014 0x0020801e
Troy Kisky71a988a2013-01-18 16:14:24 +0000185/* ESDSCR */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200186DATA 4 0x83fd9014 0x00008004
187
Troy Kisky71a988a2013-01-18 16:14:24 +0000188/* ESDCTL1: 14 ROW, 10 COL, 32Bit, SREF=8 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200189DATA 4 0x83fd9008 0xC3220000
Troy Kisky71a988a2013-01-18 16:14:24 +0000190/*
191 * ESDCFG1: tRFC:22clks, tXSR:28clks, tXP:2clks, tWTR:2clk, tRP:3clks, tMRD:2clks
192 * tRAS:8clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:11clks
193 * DATA 4 0x83fd900c 0xC33574AA
194 */
195/*
196 * micron mDDR
197 * ESDCFG1: tRFC:11clks, tXSR:19clks, tXP:1clks, tWTR:2clk, tRP:3clks, tMRD:2clks
198 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
199 * DATA 4 0x83FD900C 0x101564a8
200 */
201/*
202 * hynix mDDR
203 * ESDCFG0: tRFC:17clks, tXSR:21clks, tXP:3clks, tWTR:1clk, tRP:3clks, tMRD:2clks
204 * tRAS:7clks, tRRD:2clks, tWR:3clks, tRCD:3clks, tRC:9clks
205 */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200206DATA 4 0x83FD900C 0x704564a8
207
Troy Kisky71a988a2013-01-18 16:14:24 +0000208/* ESDSCR (mDRAM configuration finished) */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200209DATA 4 0x83FD9014 0x00000004
210
Troy Kisky71a988a2013-01-18 16:14:24 +0000211/* ESDSCR - clear "configuration request" bit */
Stefano Babicf8f8acd2010-07-06 19:32:09 +0200212DATA 4 0x83fd9014 0x00000000