Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Configuation settings for the Hitachi Solution Engine 7720 |
| 3 | * |
| 4 | * Copyright (C) 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> |
| 5 | * |
| 6 | * See file CREDITS for list of people who contributed to this |
| 7 | * project. |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License as |
| 11 | * published by the Free Software Foundation; either version 2 of |
| 12 | * the License, or (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 22 | * MA 02111-1307 USA |
| 23 | */ |
| 24 | |
| 25 | #ifndef __MS7720SE_H |
| 26 | #define __MS7720SE_H |
| 27 | |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 28 | #define CONFIG_SH 1 |
| 29 | #define CONFIG_SH3 1 |
| 30 | #define CONFIG_CPU_SH7720 1 |
| 31 | #define CONFIG_MS7720SE 1 |
| 32 | |
| 33 | #define CONFIG_CMD_FLASH |
| 34 | #define CONFIG_CMD_ENV |
| 35 | #define CONFIG_CMD_SDRAM |
| 36 | #define CONFIG_CMD_MEMORY |
| 37 | #define CONFIG_CMD_CACHE |
| 38 | #define CONFIG_CMD_PCMCIA |
| 39 | #define CONFIG_CMD_IDE |
| 40 | #define CONFIG_CMD_EXT2 |
| 41 | |
Yoshihiro Shimoda | b2b5e2b | 2007-12-03 22:58:50 +0900 | [diff] [blame] | 42 | #define CONFIG_BAUDRATE 115200 |
| 43 | #define CONFIG_BOOTARGS "console=ttySC0,115200" |
| 44 | #define CONFIG_BOOTFILE /boot/zImage |
| 45 | #define CONFIG_LOADADDR 0x8E000000 |
| 46 | |
| 47 | #define CONFIG_VERSION_VARIABLE |
| 48 | #undef CONFIG_SHOW_BOOT_PROGRESS |
| 49 | |
| 50 | /* MEMORY */ |
| 51 | #define MS7720SE_SDRAM_BASE 0x8C000000 |
| 52 | #define MS7720SE_FLASH_BASE_1 0xA0000000 |
| 53 | #define MS7720SE_FLASH_BANK_SIZE (8 * 1024 * 1024) |
| 54 | |
| 55 | #define CFG_LONGHELP /* undef to save memory */ |
| 56 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 57 | #define CFG_CBSIZE 256 /* Buffer size for input from the Console */ |
| 58 | #define CFG_PBSIZE 256 /* Buffer size for Console output */ |
| 59 | #define CFG_MAXARGS 16 /* max args accepted for monitor commands */ |
| 60 | /* Buffer size for Boot Arguments passed to kernel */ |
| 61 | #define CFG_BARGSIZE 512 |
| 62 | /* List of legal baudrate settings for this board */ |
| 63 | #define CFG_BAUDRATE_TABLE { 115200 } |
| 64 | |
| 65 | /* SCIF */ |
| 66 | #define CFG_SCIF_CONSOLE 1 |
| 67 | #define CONFIG_CONS_SCIF0 1 |
| 68 | |
| 69 | #define CFG_MEMTEST_START MS7720SE_SDRAM_BASE |
| 70 | #define CFG_MEMTEST_END (CFG_MEMTEST_START + (60 * 1024 * 1024)) |
| 71 | |
| 72 | #define CFG_SDRAM_BASE MS7720SE_SDRAM_BASE |
| 73 | #define CFG_SDRAM_SIZE (64 * 1024 * 1024) |
| 74 | |
| 75 | #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 32 * 1024 * 1024) |
| 76 | #define CFG_MONITOR_BASE MS7720SE_FLASH_BASE_1 |
| 77 | #define CFG_MONITOR_LEN (128 * 1024) |
| 78 | #define CFG_MALLOC_LEN (256 * 1024) |
| 79 | #define CFG_GBL_DATA_SIZE 256 |
| 80 | #define CFG_BOOTMAPSZ (8 * 1024 * 1024) |
| 81 | |
| 82 | |
| 83 | /* FLASH */ |
| 84 | #define CFG_FLASH_CFI |
| 85 | #define CFG_FLASH_CFI_DRIVER |
| 86 | #undef CFG_FLASH_QUIET_TEST |
| 87 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ |
| 88 | |
| 89 | #define CFG_FLASH_BASE MS7720SE_FLASH_BASE_1 |
| 90 | |
| 91 | #define CFG_MAX_FLASH_SECT 150 |
| 92 | #define CFG_MAX_FLASH_BANKS 1 |
| 93 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } |
| 94 | |
| 95 | #define CFG_ENV_IS_IN_FLASH |
| 96 | #define CFG_ENV_SECT_SIZE (64 * 1024) |
| 97 | #define CFG_ENV_SIZE CFG_ENV_SECT_SIZE |
| 98 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
| 99 | #define CFG_FLASH_ERASE_TOUT 120000 |
| 100 | #define CFG_FLASH_WRITE_TOUT 500 |
| 101 | |
| 102 | /* Board Clock */ |
| 103 | #define CONFIG_SYS_CLK_FREQ 33333333 |
| 104 | #define TMU_CLK_DIVIDER 4 /* 4 (default), 16, 64, 256 or 1024 */ |
| 105 | #define CFG_HZ (CONFIG_SYS_CLK_FREQ / TMU_CLK_DIVIDER) |
| 106 | |
| 107 | /* PCMCIA */ |
| 108 | #define CONFIG_IDE_PCMCIA 1 |
| 109 | #define CONFIG_MARUBUN_PCCARD 1 |
| 110 | #define CONFIG_PCMCIA_SLOT_A 1 |
| 111 | #define CFG_IDE_MAXDEVICE 1 |
| 112 | #define CFG_MARUBUN_MRSHPC 0xb83fffe0 |
| 113 | #define CFG_MARUBUN_MW1 0xb8400000 |
| 114 | #define CFG_MARUBUN_MW2 0xb8500000 |
| 115 | #define CFG_MARUBUN_IO 0xb8600000 |
| 116 | |
| 117 | #define CFG_PIO_MODE 1 |
| 118 | #define CFG_IDE_MAXBUS 1 |
| 119 | #define CONFIG_DOS_PARTITION 1 |
| 120 | #define CFG_ATA_BASE_ADDR CFG_MARUBUN_IO /* base address */ |
| 121 | #define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ |
| 122 | #define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ |
| 123 | #define CFG_ATA_REG_OFFSET 0 /* reg offset */ |
| 124 | #define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ |
| 125 | |
| 126 | #endif /* __MS7720SE_H */ |