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Stefano Babic3b8ac462010-06-29 11:47:48 +02001/*
2 * Porting to U-Boot:
3 *
4 * (C) Copyright 2010
5 * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
6 *
7 * Lattice's ispVME Embedded Tool to load Lattice's FPGA:
8 *
9 * Lattice Semiconductor Corp. Copyright 2009
10 *
Wolfgang Denk1a459662013-07-08 09:37:19 +020011 * SPDX-License-Identifier: GPL-2.0+
Stefano Babic3b8ac462010-06-29 11:47:48 +020012 */
13
14#ifndef _VME_OPCODE_H
15#define _VME_OPCODE_H
16
17#define VME_VERSION_NUMBER "12.1"
18
19/* Maximum declarations. */
20
21#define VMEHEXMAX 60000L /* The hex file is split 60K per file. */
22#define SCANMAX 64000L /* The maximum SDR/SIR burst. */
23
24/*
25 *
26 * Supported JTAG state transitions.
27 *
28 */
29
30#define RESET 0x00
31#define IDLE 0x01
32#define IRPAUSE 0x02
33#define DRPAUSE 0x03
34#define SHIFTIR 0x04
35#define SHIFTDR 0x05
36/* 11/15/05 Nguyen changed to support DRCAPTURE*/
37#define DRCAPTURE 0x06
38
39/*
40 * Flow control register bit definitions. A set bit indicates
41 * that the register currently exhibits the corresponding mode.
42 */
43
44#define INTEL_PRGM 0x0001 /* Intelligent programming is in effect. */
45#define CASCADE 0x0002 /* Currently splitting large SDR. */
46#define REPEATLOOP 0x0008 /* Currently executing a repeat loop. */
47#define SHIFTRIGHT 0x0080 /* The next data stream needs a right shift. */
48#define SHIFTLEFT 0x0100 /* The next data stream needs a left shift. */
49#define VERIFYUES 0x0200 /* Continue if fail is in effect. */
50
51/*
52 * DataType register bit definitions. A set bit indicates
53 * that the register currently holds the corresponding type of data.
54 */
55
56#define EXPRESS 0x0001 /* Simultaneous program and verify. */
57#define SIR_DATA 0x0002 /* SIR is the active SVF command. */
58#define SDR_DATA 0x0004 /* SDR is the active SVF command. */
59#define COMPRESS 0x0008 /* Data is compressed. */
60#define TDI_DATA 0x0010 /* TDI data is present. */
61#define TDO_DATA 0x0020 /* TDO data is present. */
62#define MASK_DATA 0x0040 /* MASK data is present. */
63#define HEAP_IN 0x0080 /* Data is from the heap. */
64#define LHEAP_IN 0x0200 /* Data is from intel data buffer. */
65#define VARIABLE 0x0400 /* Data is from a declared variable. */
66#define CRC_DATA 0x0800 /* CRC data is pressent. */
67#define CMASK_DATA 0x1000 /* CMASK data is pressent. */
68#define RMASK_DATA 0x2000 /* RMASK data is pressent. */
69#define READ_DATA 0x4000 /* READ data is pressent. */
70#define DMASK_DATA 0x8000 /* DMASK data is pressent. */
71
72/*
73 *
74 * Pin opcodes.
75 *
76 */
77
78#define signalENABLE 0x1C /* ispENABLE pin. */
79#define signalTMS 0x1D /* TMS pin. */
80#define signalTCK 0x1E /* TCK pin. */
81#define signalTDI 0x1F /* TDI pin. */
82#define signalTRST 0x20 /* TRST pin. */
83
84/*
85 *
86 * Supported vendors.
87 *
88 */
89
90#define VENDOR 0x56
91#define LATTICE 0x01
92#define ALTERA 0x02
93#define XILINX 0x03
94
95/*
96 * Opcode definitions.
97 *
98 * Note: opcodes must be unique.
99 */
100
101#define ENDDATA 0x00 /* The end of the current SDR data stream. */
102#define RUNTEST 0x01 /* The duration to stay at the stable state. */
103#define ENDDR 0x02 /* The stable state after SDR. */
104#define ENDIR 0x03 /* The stable state after SIR. */
105#define ENDSTATE 0x04 /* The stable state after RUNTEST. */
106#define TRST 0x05 /* Assert the TRST pin. */
107#define HIR 0x06 /*
108 * The sum of the IR bits of the
109 * leading devices.
110 */
111#define TIR 0x07 /*
112 * The sum of the IR bits of the trailing
113 * devices.
114 */
115#define HDR 0x08 /* The number of leading devices. */
116#define TDR 0x09 /* The number of trailing devices. */
117#define ispEN 0x0A /* Assert the ispEN pin. */
118#define FREQUENCY 0x0B /*
119 * The maximum clock rate to run the JTAG state
120 * machine.
121 */
122#define STATE 0x10 /* Move to the next stable state. */
123#define SIR 0x11 /* The instruction stream follows. */
124#define SDR 0x12 /* The data stream follows. */
125#define TDI 0x13 /* The following data stream feeds into
126 the device. */
127#define TDO 0x14 /*
128 * The following data stream is compared against
129 * the device.
130 */
131#define MASK 0x15 /* The following data stream is used as mask. */
132#define XSDR 0x16 /*
133 * The following data stream is for simultaneous
134 * program and verify.
135 */
136#define XTDI 0x17 /* The following data stream is for shift in
137 * only. It must be stored for the next
138 * XSDR.
139 */
140#define XTDO 0x18 /*
141 * There is not data stream. The data stream
142 * was stored from the previous XTDI.
143 */
144#define MEM 0x19 /*
145 * The maximum memory needed to allocate in
146 * order hold one row of data.
147 */
148#define WAIT 0x1A /* The duration of delay to observe. */
149#define TCK 0x1B /* The number of TCK pulses. */
150#define SHR 0x23 /*
151 * Set the flow control register for
152 * right shift
153 */
154#define SHL 0x24 /*
155 * Set the flow control register for left shift.
156 */
157#define HEAP 0x32 /* The memory size needed to hold one loop. */
158#define REPEAT 0x33 /* The beginning of the loop. */
159#define LEFTPAREN 0x35 /* The beginning of data following the loop. */
160#define VAR 0x55 /* Plac holder for loop data. */
161#define SEC 0x1C /*
162 * The delay time in seconds that must be
163 * observed.
164 */
165#define SMASK 0x1D /* The mask for TDI data. */
166#define MAX_WAIT 0x1E /* The absolute maximum wait time. */
167#define ON 0x1F /* Assert the targeted pin. */
168#define OFF 0x20 /* Dis-assert the targeted pin. */
169#define SETFLOW 0x30 /* Change the flow control register. */
170#define RESETFLOW 0x31 /* Clear the flow control register. */
171
172#define CRC 0x47 /*
173 * The following data stream is used for CRC
174 * calculation.
175 */
176#define CMASK 0x48 /*
177 * The following data stream is used as mask
178 * for CRC calculation.
179 */
180#define RMASK 0x49 /*
181 * The following data stream is used as mask
182 * for read and save.
183 */
184#define READ 0x50 /*
185 * The following data stream is used for read
186 * and save.
187 */
188#define ENDLOOP 0x59 /* The end of the repeat loop. */
189#define SECUREHEAP 0x60 /* Used to secure the HEAP opcode. */
190#define VUES 0x61 /* Support continue if fail. */
191#define DMASK 0x62 /*
192 * The following data stream is used for dynamic
193 * I/O.
194 */
195#define COMMENT 0x63 /* Support SVF comments in the VME file. */
196#define HEADER 0x64 /* Support header in VME file. */
197#define FILE_CRC 0x65 /* Support crc-protected VME file. */
198#define LCOUNT 0x66 /* Support intelligent programming. */
199#define LDELAY 0x67 /* Support intelligent programming. */
200#define LSDR 0x68 /* Support intelligent programming. */
201#define LHEAP 0x69 /*
202 * Memory needed to hold intelligent data
203 * buffer
204 */
205#define CONTINUE 0x70 /* Allow continuation. */
206#define LVDS 0x71 /* Support LVDS. */
207#define ENDVME 0x7F /* End of the VME file. */
208#define ENDFILE 0xFF /* End of file. */
209
210/*
211 *
212 * ispVM Embedded Return Codes.
213 *
214 */
215
216#define VME_VERIFICATION_FAILURE -1
217#define VME_FILE_READ_FAILURE -2
218#define VME_VERSION_FAILURE -3
219#define VME_INVALID_FILE -4
220#define VME_ARGUMENT_FAILURE -5
221#define VME_CRC_FAILURE -6
222
223#define g_ucPinTDI 0x01
224#define g_ucPinTCK 0x02
225#define g_ucPinTMS 0x04
226#define g_ucPinENABLE 0x08
227#define g_ucPinTRST 0x10
228
229/*
230 *
231 * Type definitions.
232 *
233 */
234
235/* Support LVDS */
236typedef struct {
237 unsigned short usPositiveIndex;
238 unsigned short usNegativeIndex;
239 unsigned char ucUpdate;
240} LVDSPair;
241
242typedef enum {
243 min_lattice_iface_type, /* insert all new types after this */
244 lattice_jtag_mode, /* jtag/tap */
245 max_lattice_iface_type /* insert all new types before this */
246} Lattice_iface;
247
248typedef enum {
249 min_lattice_type,
250 Lattice_XP2, /* Lattice XP2 Family */
251 max_lattice_type /* insert all new types before this */
252} Lattice_Family;
253
254typedef struct {
255 Lattice_Family family; /* part type */
256 Lattice_iface iface; /* interface type */
257 size_t size; /* bytes of data part can accept */
258 void *iface_fns; /* interface function table */
259 void *base; /* base interface address */
260 int cookie; /* implementation specific cookie */
261 char *desc; /* description string */
262} Lattice_desc; /* end, typedef Altera_desc */
263
Stefano Babic3b8ac462010-06-29 11:47:48 +0200264/* Board specific implementation specific function types */
265typedef void (*Lattice_jtag_init)(void);
266typedef void (*Lattice_jtag_set_tdi)(int v);
267typedef void (*Lattice_jtag_set_tms)(int v);
268typedef void (*Lattice_jtag_set_tck)(int v);
269typedef int (*Lattice_jtag_get_tdo)(void);
270
271typedef struct {
272 Lattice_jtag_init jtag_init;
273 Lattice_jtag_set_tdi jtag_set_tdi;
274 Lattice_jtag_set_tms jtag_set_tms;
275 Lattice_jtag_set_tck jtag_set_tck;
276 Lattice_jtag_get_tdo jtag_get_tdo;
277} lattice_board_specific_func;
278
279void writePort(unsigned char pins, unsigned char value);
280unsigned char readPort(void);
281void sclock(void);
282void ispVMDelay(unsigned short int a_usMicroSecondDelay);
283void calibration(void);
284
Wolfgang Denkfb2d6ef2011-08-05 02:26:31 +0000285int lattice_load(Lattice_desc *desc, const void *buf, size_t bsize);
286int lattice_dump(Lattice_desc *desc, const void *buf, size_t bsize);
Stefano Babic3b8ac462010-06-29 11:47:48 +0200287int lattice_info(Lattice_desc *desc);
288
289void ispVMStart(void);
290void ispVMEnd(void);
Stefano Babicc56ded62010-10-19 09:22:23 +0200291extern void ispVMFreeMem(void);
Stefano Babic3b8ac462010-06-29 11:47:48 +0200292signed char ispVMCode(void);
293void ispVMDelay(unsigned short int a_usMicroSecondDelay);
294void ispVMCalculateCRC32(unsigned char a_ucData);
295unsigned char GetByte(void);
296void writePort(unsigned char pins, unsigned char value);
297unsigned char readPort(void);
298void sclock(void);
299#endif