| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 1 | /* |
| Andy Fleming | 61a21e9 | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 2 | * Copyright 2004, 2007 Freescale Semiconductor. |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 3 | * Copyright(c) 2003 Motorola Inc. |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #ifndef __MPC85xx_H__ |
| 7 | #define __MPC85xx_H__ |
| 8 | |
| Andy Fleming | 61a21e9 | 2007-08-14 01:34:21 -0500 | [diff] [blame] | 9 | /* define for common ppc_asm.tmpl */ |
| 10 | #define EXC_OFF_SYS_RESET 0x100 /* System reset */ |
| 11 | #define _START_OFFSET 0 |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 12 | |
| 13 | #if defined(CONFIG_E500) |
| 14 | #include <e500.h> |
| 15 | #endif |
| 16 | |
| wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 17 | /* |
| 18 | * SCCR - System Clock Control Register, 9-8 |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 19 | */ |
| wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 20 | #define SCCR_CLPD 0x00000004 /* CPM Low Power Disable */ |
| 21 | #define SCCR_DFBRG_MSK 0x00000003 /* Division by BRGCLK Mask */ |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 22 | #define SCCR_DFBRG_SHIFT 0 |
| 23 | |
| wdenk | 0ac6f8b | 2004-07-09 23:27:13 +0000 | [diff] [blame] | 24 | #define SCCR_DFBRG00 0x00000000 /* BRGCLK division by 4 */ |
| 25 | #define SCCR_DFBRG01 0x00000001 /* BRGCLK div by 16 (normal) */ |
| 26 | #define SCCR_DFBRG10 0x00000002 /* BRGCLK division by 64 */ |
| 27 | #define SCCR_DFBRG11 0x00000003 /* BRGCLK division by 256 */ |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 28 | |
| wdenk | 42d1f03 | 2003-10-15 23:53:47 +0000 | [diff] [blame] | 29 | #endif /* __MPC85xx_H__ */ |