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Michal Simek18a952c2018-03-27 10:36:39 +02001// SPDX-License-Identifier: GPL-2.0+
Michal Simekee4983f2017-12-08 14:50:42 +01002/*
3 * Clock specification for Xilinx ZynqMP
4 *
Michal Simekaf045162021-06-01 16:40:43 +02005 * (C) Copyright 2017 - 2021, Xilinx, Inc.
Michal Simekee4983f2017-12-08 14:50:42 +01006 *
7 * Michal Simek <michal.simek@xilinx.com>
Michal Simekee4983f2017-12-08 14:50:42 +01008 */
9
Michal Simek039c7402019-10-14 15:42:03 +020010#include <dt-bindings/clock/xlnx-zynqmp-clk.h>
Michal Simekee4983f2017-12-08 14:50:42 +010011/ {
12 fclk0: fclk0 {
Michal Simek039c7402019-10-14 15:42:03 +020013 status = "okay";
Michal Simekee4983f2017-12-08 14:50:42 +010014 compatible = "xlnx,fclk";
Michal Simek039c7402019-10-14 15:42:03 +020015 clocks = <&zynqmp_clk PL0_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +010016 };
17
18 fclk1: fclk1 {
Michal Simek039c7402019-10-14 15:42:03 +020019 status = "okay";
Michal Simekee4983f2017-12-08 14:50:42 +010020 compatible = "xlnx,fclk";
Michal Simek039c7402019-10-14 15:42:03 +020021 clocks = <&zynqmp_clk PL1_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +010022 };
23
24 fclk2: fclk2 {
Michal Simek039c7402019-10-14 15:42:03 +020025 status = "okay";
Michal Simekee4983f2017-12-08 14:50:42 +010026 compatible = "xlnx,fclk";
Michal Simek039c7402019-10-14 15:42:03 +020027 clocks = <&zynqmp_clk PL2_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +010028 };
29
30 fclk3: fclk3 {
Michal Simek039c7402019-10-14 15:42:03 +020031 status = "okay";
Michal Simekee4983f2017-12-08 14:50:42 +010032 compatible = "xlnx,fclk";
Michal Simek039c7402019-10-14 15:42:03 +020033 clocks = <&zynqmp_clk PL3_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +010034 };
35
36 pss_ref_clk: pss_ref_clk {
37 u-boot,dm-pre-reloc;
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <33333333>;
41 };
42
43 video_clk: video_clk {
44 u-boot,dm-pre-reloc;
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
47 clock-frequency = <27000000>;
48 };
49
50 pss_alt_ref_clk: pss_alt_ref_clk {
51 u-boot,dm-pre-reloc;
52 compatible = "fixed-clock";
53 #clock-cells = <0>;
54 clock-frequency = <0>;
55 };
56
57 gt_crx_ref_clk: gt_crx_ref_clk {
58 u-boot,dm-pre-reloc;
59 compatible = "fixed-clock";
60 #clock-cells = <0>;
61 clock-frequency = <108000000>;
62 };
63
64 aux_ref_clk: aux_ref_clk {
65 u-boot,dm-pre-reloc;
66 compatible = "fixed-clock";
67 #clock-cells = <0>;
68 clock-frequency = <27000000>;
69 };
Michal Simekee4983f2017-12-08 14:50:42 +010070};
71
Michal Simek039c7402019-10-14 15:42:03 +020072&zynqmp_firmware {
73 zynqmp_clk: clock-controller {
74 u-boot,dm-pre-reloc;
75 #clock-cells = <1>;
76 compatible = "xlnx,zynqmp-clk";
77 clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>,
78 <&aux_ref_clk>, <&gt_crx_ref_clk>;
79 clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk",
80 "aux_ref_clk", "gt_crx_ref_clk";
81 };
82};
83
Michal Simekee4983f2017-12-08 14:50:42 +010084&can0 {
Michal Simek039c7402019-10-14 15:42:03 +020085 clocks = <&zynqmp_clk CAN0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +010086};
87
88&can1 {
Michal Simek039c7402019-10-14 15:42:03 +020089 clocks = <&zynqmp_clk CAN1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +010090};
91
92&cpu0 {
Michal Simek039c7402019-10-14 15:42:03 +020093 clocks = <&zynqmp_clk ACPU>;
Michal Simekee4983f2017-12-08 14:50:42 +010094};
95
96&fpd_dma_chan1 {
Michal Simek039c7402019-10-14 15:42:03 +020097 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +010098};
99
100&fpd_dma_chan2 {
Michal Simek039c7402019-10-14 15:42:03 +0200101 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100102};
103
104&fpd_dma_chan3 {
Michal Simek039c7402019-10-14 15:42:03 +0200105 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100106};
107
108&fpd_dma_chan4 {
Michal Simek039c7402019-10-14 15:42:03 +0200109 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100110};
111
112&fpd_dma_chan5 {
Michal Simek039c7402019-10-14 15:42:03 +0200113 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100114};
115
116&fpd_dma_chan6 {
Michal Simek039c7402019-10-14 15:42:03 +0200117 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100118};
119
120&fpd_dma_chan7 {
Michal Simek039c7402019-10-14 15:42:03 +0200121 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100122};
123
124&fpd_dma_chan8 {
Michal Simek039c7402019-10-14 15:42:03 +0200125 clocks = <&zynqmp_clk GDMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100126};
127
128&gpu {
Michal Simek039c7402019-10-14 15:42:03 +0200129 clocks = <&zynqmp_clk GPU_REF>, <&zynqmp_clk GPU_PP0_REF>, <&zynqmp_clk GPU_PP1_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100130};
131
132&lpd_dma_chan1 {
Michal Simek039c7402019-10-14 15:42:03 +0200133 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100134};
135
136&lpd_dma_chan2 {
Michal Simek039c7402019-10-14 15:42:03 +0200137 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100138};
139
140&lpd_dma_chan3 {
Michal Simek039c7402019-10-14 15:42:03 +0200141 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100142};
143
144&lpd_dma_chan4 {
Michal Simek039c7402019-10-14 15:42:03 +0200145 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100146};
147
148&lpd_dma_chan5 {
Michal Simek039c7402019-10-14 15:42:03 +0200149 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100150};
151
152&lpd_dma_chan6 {
Michal Simek039c7402019-10-14 15:42:03 +0200153 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100154};
155
156&lpd_dma_chan7 {
Michal Simek039c7402019-10-14 15:42:03 +0200157 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100158};
159
160&lpd_dma_chan8 {
Michal Simek039c7402019-10-14 15:42:03 +0200161 clocks = <&zynqmp_clk ADMA_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100162};
163
164&nand0 {
Michal Simek039c7402019-10-14 15:42:03 +0200165 clocks = <&zynqmp_clk NAND_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100166};
167
168&gem0 {
Michal Simekb0f36d52020-01-09 14:15:07 +0100169 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM0_REF>,
170 <&zynqmp_clk GEM0_TX>, <&zynqmp_clk GEM0_RX>,
171 <&zynqmp_clk GEM_TSU>;
Michal Simekee4983f2017-12-08 14:50:42 +0100172};
173
174&gem1 {
Michal Simekb0f36d52020-01-09 14:15:07 +0100175 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM1_REF>,
176 <&zynqmp_clk GEM1_TX>, <&zynqmp_clk GEM1_RX>,
177 <&zynqmp_clk GEM_TSU>;
Michal Simekee4983f2017-12-08 14:50:42 +0100178};
179
180&gem2 {
Michal Simekb0f36d52020-01-09 14:15:07 +0100181 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM2_REF>,
182 <&zynqmp_clk GEM2_TX>, <&zynqmp_clk GEM2_RX>,
183 <&zynqmp_clk GEM_TSU>;
Michal Simekee4983f2017-12-08 14:50:42 +0100184};
185
186&gem3 {
Michal Simekb0f36d52020-01-09 14:15:07 +0100187 clocks = <&zynqmp_clk LPD_LSBUS>, <&zynqmp_clk GEM3_REF>,
188 <&zynqmp_clk GEM3_TX>, <&zynqmp_clk GEM3_RX>,
189 <&zynqmp_clk GEM_TSU>;
Michal Simekee4983f2017-12-08 14:50:42 +0100190};
191
192&gpio {
Michal Simek039c7402019-10-14 15:42:03 +0200193 clocks = <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100194};
195
196&i2c0 {
Michal Simek039c7402019-10-14 15:42:03 +0200197 clocks = <&zynqmp_clk I2C0_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100198};
199
200&i2c1 {
Michal Simek039c7402019-10-14 15:42:03 +0200201 clocks = <&zynqmp_clk I2C1_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100202};
203
204&pcie {
Michal Simek039c7402019-10-14 15:42:03 +0200205 clocks = <&zynqmp_clk PCIE_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100206};
207
208&qspi {
Michal Simek039c7402019-10-14 15:42:03 +0200209 clocks = <&zynqmp_clk QSPI_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100210};
211
212&sata {
Michal Simek039c7402019-10-14 15:42:03 +0200213 clocks = <&zynqmp_clk SATA_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100214};
215
216&sdhci0 {
Michal Simek039c7402019-10-14 15:42:03 +0200217 clocks = <&zynqmp_clk SDIO0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka3efa532022-02-23 16:17:39 +0100218 assigned-clocks = <&zynqmp_clk SDIO0_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100219};
220
221&sdhci1 {
Michal Simek039c7402019-10-14 15:42:03 +0200222 clocks = <&zynqmp_clk SDIO1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simeka3efa532022-02-23 16:17:39 +0100223 assigned-clocks = <&zynqmp_clk SDIO1_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100224};
225
226&spi0 {
Michal Simek039c7402019-10-14 15:42:03 +0200227 clocks = <&zynqmp_clk SPI0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100228};
229
230&spi1 {
Michal Simek039c7402019-10-14 15:42:03 +0200231 clocks = <&zynqmp_clk SPI1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100232};
233
Rajan Vajaecb4d742018-04-25 05:34:04 -0700234&ttc0 {
Michal Simek039c7402019-10-14 15:42:03 +0200235 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vajaecb4d742018-04-25 05:34:04 -0700236};
237
238&ttc1 {
Michal Simek039c7402019-10-14 15:42:03 +0200239 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vajaecb4d742018-04-25 05:34:04 -0700240};
241
242&ttc2 {
Michal Simek039c7402019-10-14 15:42:03 +0200243 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vajaecb4d742018-04-25 05:34:04 -0700244};
245
246&ttc3 {
Michal Simek039c7402019-10-14 15:42:03 +0200247 clocks = <&zynqmp_clk LPD_LSBUS>;
Rajan Vajaecb4d742018-04-25 05:34:04 -0700248};
249
Michal Simekee4983f2017-12-08 14:50:42 +0100250&uart0 {
Michal Simek039c7402019-10-14 15:42:03 +0200251 clocks = <&zynqmp_clk UART0_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100252};
253
254&uart1 {
Michal Simek039c7402019-10-14 15:42:03 +0200255 clocks = <&zynqmp_clk UART1_REF>, <&zynqmp_clk LPD_LSBUS>;
Michal Simekee4983f2017-12-08 14:50:42 +0100256};
257
258&usb0 {
Michal Simek039c7402019-10-14 15:42:03 +0200259 clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
Michal Simeka3efa532022-02-23 16:17:39 +0100260 assigned-clocks = <&zynqmp_clk USB0_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100261};
262
Piyush Mehta1bff67e2022-08-23 15:03:31 +0200263&dwc3_0 {
264 clocks = <&zynqmp_clk USB3_DUAL_REF>;
265};
266
Michal Simekee4983f2017-12-08 14:50:42 +0100267&usb1 {
Michal Simek039c7402019-10-14 15:42:03 +0200268 clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
Michal Simeka3efa532022-02-23 16:17:39 +0100269 assigned-clocks = <&zynqmp_clk USB1_BUS_REF>, <&zynqmp_clk USB3_DUAL_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100270};
271
Piyush Mehta1bff67e2022-08-23 15:03:31 +0200272&dwc3_1 {
273 clocks = <&zynqmp_clk USB3_DUAL_REF>;
274};
275
Michal Simekee4983f2017-12-08 14:50:42 +0100276&watchdog0 {
Michal Simek039c7402019-10-14 15:42:03 +0200277 clocks = <&zynqmp_clk WDT>;
Michal Simekee4983f2017-12-08 14:50:42 +0100278};
279
Michal Simek2038e462018-07-18 09:25:43 +0200280&lpd_watchdog {
281 clocks = <&zynqmp_clk LPD_WDT>;
282};
283
Michal Simekee4983f2017-12-08 14:50:42 +0100284&xilinx_ams {
Michal Simek039c7402019-10-14 15:42:03 +0200285 clocks = <&zynqmp_clk AMS_REF>;
Michal Simekee4983f2017-12-08 14:50:42 +0100286};
287
Michal Simekce906542020-11-26 14:25:02 +0100288&zynqmp_pcap {
289 clocks = <&zynqmp_clk PCAP>;
Michal Simek04437de2020-02-18 09:24:08 +0100290};
291
Michal Simekce906542020-11-26 14:25:02 +0100292&zynqmp_dpdma {
Michal Simek039c7402019-10-14 15:42:03 +0200293 clocks = <&zynqmp_clk DPDMA_REF>;
Michal Simek59e1bdd2022-02-23 16:17:38 +0100294 assigned-clocks = <&zynqmp_clk DPDMA_REF>; /* apll */
Michal Simekee4983f2017-12-08 14:50:42 +0100295};
296
Michal Simekce906542020-11-26 14:25:02 +0100297&zynqmp_dpsub {
298 clocks = <&zynqmp_clk TOPSW_LSBUS>,
299 <&zynqmp_clk DP_AUDIO_REF>,
300 <&zynqmp_clk DP_VIDEO_REF>;
Michal Simek59e1bdd2022-02-23 16:17:38 +0100301 assigned-clocks = <&zynqmp_clk DP_STC_REF>,
302 <&zynqmp_clk DP_AUDIO_REF>,
303 <&zynqmp_clk DP_VIDEO_REF>; /* rpll, rpll, vpll */
Nava kishore Manne21620992019-10-18 18:07:32 +0200304};