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wdenk0f8c9762002-08-19 11:57:05 +00001 /*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T MBX board.
4 * Copied from the FADS stuff, which was originally copied from the MBX stuff!
5 * Magnus Damm added defines for 8xxrom and extended bd_info.
6 * Helmut Buchsbaum added bitvalues for BCSRx
7 * Rob Taylor coverted it back to MBX
8 *
9 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
10 */
11
12/* ------------------------------------------------------------------------- */
13
14/*
15 * board/config.h - configuration options, board specific
16 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/*
22 * High Level Configuration Options
23 * (easy to change)
24 */
25#include <mpc8xx_irq.h>
26
27#define CONFIG_MPC860 1
28#define CONFIG_MPC860T 1
29#define CONFIG_MBX 1
30
31#define CONFIG_8xx_CPUCLOCK 40
32#define CONFIG_8xx_BUSCLOCK (CONFIG_8xx_CPUCLOCK)
33#define TARGET_SYSTEM_FREQUENCY 40
34
35#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
36#undef CONFIG_8xx_CONS_SMC2
37#define CONFIG_BAUDRATE 9600
38
39#define MPC8XX_FACT 10 /* Multiply by 10 */
40#define MPC8XX_XIN 40000000 /* 50 MHz in */
41#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
42
43#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
44
45#if 1
46#define CONFIG_8xx_BOOTDELAY -1 /* autoboot disabled */
47#define CONFIG_8xx_TFTP_MODE
48#else
49#define CONFIG_8xx_BOOTDELAY 5 /* autoboot after 5 seconds */
50#undef CONFIG_8xx_TFTP_MODE
51#endif
52
53#define CONFIG_DRAM_SPEED (CONFIG_8xx_BUSCLOCK) /* MHz */
54#define CONFIG_BOOTCOMMAND "bootm FE020000" /* autoboot command */
55#define CONFIG_BOOTARGS " "
56/*
57 * Miscellaneous configurable options
58 */
59#undef CFG_LONGHELP /* undef to save memory */
60#define CFG_PROMPT ":>" /* Monitor Command Prompt */
61#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
62#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
63#define CFG_MAXARGS 16 /* max number of command args */
64#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
65
66#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
67#define CFG_MEMTEST_END 0x0800000 /* 4 ... 8 MB in DRAM */
68
69#define CFG_LOAD_ADDR 0x100000 /* default load address */
70
71#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
72
73#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
74
75/*
76 * Low Level Configuration Settings
77 * (address mappings, register initial values, etc.)
78 * You should know what you are doing if you make changes here.
79 */
80/*-----------------------------------------------------------------------
81 * Internal Memory Mapped Register
82 */
83#define CFG_IMMR 0xFFA00000
84#define CFG_IMMR_SIZE ((uint)(64 * 1024))
85#define CFG_NVRAM_BASE 0xFA000000 /* NVRAM */
86#define CFG_NVRAM_OR 0xffe00000 /* w/o speed dependent flags!! */
87#define CFG_CSR_BASE 0xFA100000 /* Control/Status Registers */
88#define CFG_PCIMEM_BASE 0x80000000 /* PCI I/O and Memory Spaces */
89#define CFG_PCIMEM_OR 0xA0000108
90#define CFG_PCIBRIDGE_BASE 0xFA210000 /* PCI-Bus Bridge Registers */
91#define CFG_PCIBRIDGE_OR 0xFFFF0108
92
93/*-----------------------------------------------------------------------
94 * Definitions for initial stack pointer and data area (in DPRAM)
95 */
96#define CFG_INIT_RAM_ADDR CFG_IMMR
97#define CFG_INIT_RAM_END 0x2f00 /* End of used area in DPRAM */
98#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
99#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
100#define CFG_INIT_VPD_SIZE 256 /* size in bytes reserved for vpd buffer */
101#define CFG_INIT_VPD_OFFSET (CFG_GBL_DATA_OFFSET - CFG_INIT_VPD_SIZE)
102#define CFG_INIT_SP_OFFSET (CFG_INIT_VPD_OFFSET-8)
103
104/*-----------------------------------------------------------------------
105 * Offset in DPMEM where we keep the VPD data
106 */
107#define CFG_DPRAMVPD (CFG_INIT_VPD_OFFSET - 0x2000)
108
109/*-----------------------------------------------------------------------
110 * Start addresses for the final memory configuration
111 * (Set up by the startup code)
112 * Please note that CFG_SDRAM_BASE _must_ start at 0
113 */
114#define CFG_SDRAM_BASE 0x00000000
115#define CFG_FLASH_BASE 0x00000000
116/*0xFE000000*/
117#define CFG_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
118#define CFG_MONITOR_BASE CFG_FLASH_BASE
119#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
120#define CFG_HWINFO_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN - CFG_HWINFO_LEN)
121#define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */
122
123/*
124 * For booting Linux, the board info and command line data
125 * have to be in the first 8 MB of memory, since this is
126 * the maximum mapped by the Linux kernel during initialization.
127 */
128#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
129
130/*-----------------------------------------------------------------------
131 * FLASH organization
132 */
133#define CFG_MAX_FLASH_BANKS 4 /* max number of memory banks */
134#define CFG_MAX_FLASH_SECT 16 /* max number of sectors on one chip */
135
136#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
137#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
138
139/*-----------------------------------------------------------------------
140 * NVRAM Configuration
141 *
142 * Note: the MBX is special because there is already a firmware on this
143 * board: EPPC-Bug from Motorola. To avoid collisions in NVRAM Usage, we
144 * access the NVRAM at the offset 0x1000.
145 */
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200146#define CONFIG_ENV_IS_IN_NVRAM 1 /* turn on NVRAM env feature */
wdenk0f8c9762002-08-19 11:57:05 +0000147#define CFG_ENV_ADDR (CFG_NVRAM_BASE + 0x1000)
148#define CFG_ENV_SIZE 0x1000
149
150/*-----------------------------------------------------------------------
151 * Cache Configuration
152 */
153#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger8353e132007-07-08 14:14:17 -0500154#if defined(CONFIG_CMD_KGDB)
wdenk0f8c9762002-08-19 11:57:05 +0000155#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
156#endif
157
158/*-----------------------------------------------------------------------
159 * SYPCR - System Protection Control 11-9
160 * SYPCR can only be written once after reset!
161 *-----------------------------------------------------------------------
162 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
163 */
164#if defined(CONFIG_WATCHDOG)
165#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
166 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
167#else
168#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF)
169#endif
170
171/*-----------------------------------------------------------------------
172 * SIUMCR - SIU Module Configuration 11-6
173 *-----------------------------------------------------------------------
174 * PCMCIA config., multi-function pin tri-state
175 */
176#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DPC | SIUMCR_MLRC10 | SIUMCR_SEME)
177
178/*-----------------------------------------------------------------------
179 * TBSCR - Time Base Status and Control 11-26
180 *-----------------------------------------------------------------------
181 * Clear Reference Interrupt Status, Timebase freezing enabled
182 */
183#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
184
185/*-----------------------------------------------------------------------
186 * PISCR - Periodic Interrupt Status and Control 11-31
187 *-----------------------------------------------------------------------
188 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
189 */
190#define CFG_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
191
192/*-----------------------------------------------------------------------
193 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
194 *-----------------------------------------------------------------------
195 * Reset PLL lock status sticky bit, timer expired status bit and timer
196 * interrupt status bit - leave PLL multiplication factor unchanged !
197 */
198#define CFG_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
199
200/*-----------------------------------------------------------------------
201 * SCCR - System Clock and reset Control Register 15-27
202 *-----------------------------------------------------------------------
203 * Set clock output, timebase and RTC source and divider,
204 * power management and some other internal clocks
205 */
206#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL)
207#define CFG_SCCR SCCR_TBS
208
209 /*-----------------------------------------------------------------------
210 *
211 *-----------------------------------------------------------------------
212 *
213 */
214#define CFG_DER 0
215
216/* Because of the way the 860 starts up and assigns CS0 the
217* entire address space, we have to set the memory controller
218* differently. Normally, you write the option register
219* first, and then enable the chip select by writing the
220* base register. For CS0, you must write the base register
221* first, followed by the option register.
222*/
223
224/*
225 * Init Memory Controller:
226 *
227 * BR0/1 and OR0/1 (FLASH)
228 */
229/* the other CS:s are determined by looking at parameters in BCSRx */
230
231
232#define BCSR_ADDR ((uint) 0xFF010000)
233#define BCSR_SIZE ((uint)(64 * 1024))
234
235#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0 */
236#define FLASH_BASE1_PRELIM 0xFF010000 /* FLASH bank #0 */
237
238#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
239#define CFG_PRELIM_OR_AM 0xFFF00000 /* OR addr mask */
240
241/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
242#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
243
244#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH)
245#define CFG_OR0_PRELIM (0xFF800000 | OR_CSNT_SAM | OR_BI | OR_SCY_3_CLK) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
246#define CFG_BR0_PRELIM (0xFE000000 | BR_V )
247
248/* BCSRx - Board Control and Status Registers */
249#define CFG_OR1_REMAP CFG_OR0_REMAP
250#define CFG_OR1_PRELIM 0xFFC00000 | OR_ACS_DIV4
251#define CFG_BR1_PRELIM (0x00000000 | BR_MS_UPMA | BR_V )
252
253
254/*
255 * Memory Periodic Timer Prescaler
256 */
257
258/* periodic timer for refresh */
259#define CFG_MAMR_PTA 97 /* start with divider for 100 MHz */
260
261/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
262#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
263#define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
264
265/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
266#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
267#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
268
269/*
270 * MAMR settings for SDRAM
271 */
272
273/* 8 column SDRAM */
274#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
275 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
276 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
277/* 9 column SDRAM */
278#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
279 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
280 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
281
282#define CFG_MAMR 0x13821000
283/*
284 * Internal Definitions
285 *
286 * Boot Flags
287 */
288#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
289#define BOOTFLAG_WARM 0x02 /* Software reboot */
290
291
292/* values according to the manual */
293
294
295#define PCMCIA_MEM_ADDR ((uint)0xff020000)
296#define PCMCIA_MEM_SIZE ((uint)(64 * 1024))
297
298#define BCSR0 ((uint) (BCSR_ADDR + 00))
299#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
300#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
301#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
302#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
303
304/* FADS bitvalues by Helmut Buchsbaum
305 * see MPC8xxADS User's Manual for a proper description
306 * of the following structures
307 */
308
309#define BCSR0_ERB ((uint)0x80000000)
310#define BCSR0_IP ((uint)0x40000000)
311#define BCSR0_BDIS ((uint)0x10000000)
312#define BCSR0_BPS_MASK ((uint)0x0C000000)
313#define BCSR0_ISB_MASK ((uint)0x01800000)
314#define BCSR0_DBGC_MASK ((uint)0x00600000)
315#define BCSR0_DBPC_MASK ((uint)0x00180000)
316#define BCSR0_EBDF_MASK ((uint)0x00060000)
317
318#define BCSR1_FLASH_EN ((uint)0x80000000)
319#define BCSR1_DRAM_EN ((uint)0x40000000)
320#define BCSR1_ETHEN ((uint)0x20000000)
321#define BCSR1_IRDEN ((uint)0x10000000)
322#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
323#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
324#define BCSR1_BCSR_EN ((uint)0x02000000)
325#define BCSR1_RS232EN_1 ((uint)0x01000000)
326#define BCSR1_PCCEN ((uint)0x00800000)
327#define BCSR1_PCCVCC0 ((uint)0x00400000)
328#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
329#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
330#define BCSR1_RS232EN_2 ((uint)0x00040000)
331#define BCSR1_SDRAM_EN ((uint)0x00020000)
332#define BCSR1_PCCVCC1 ((uint)0x00010000)
333
334#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
335#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
336#define BCSR2_DRAM_PD_SHIFT (23)
337#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
338#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
339
340#define BCSR3_DBID_MASK ((ushort)0x3800)
341#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
342#define BCSR3_BREVNR0 ((ushort)0x0080)
343#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
344#define BCSR3_BREVN1 ((ushort)0x0008)
345#define BCSR3_BREVN2_MASK ((ushort)0x0003)
346
347#define BCSR4_ETHLOOP ((uint)0x80000000)
348#define BCSR4_TFPLDL ((uint)0x40000000)
349#define BCSR4_TPSQEL ((uint)0x20000000)
350#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
351#ifdef CONFIG_MPC823
352#define BCSR4_USB_EN ((uint)0x08000000)
353#endif /* CONFIG_MPC823 */
354#ifdef CONFIG_MPC860SAR
355#define BCSR4_UTOPIA_EN ((uint)0x08000000)
356#endif /* CONFIG_MPC860SAR */
357#ifdef CONFIG_MPC860T
358#define BCSR4_FETH_EN ((uint)0x08000000)
359#endif /* CONFIG_MPC860T */
360#define BCSR4_USB_SPEED ((uint)0x04000000)
361#define BCSR4_VCCO ((uint)0x02000000)
362#define BCSR4_VIDEO_ON ((uint)0x00800000)
363#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
364#define BCSR4_VIDEO_RST ((uint)0x00200000)
365#define BCSR4_MODEM_EN ((uint)0x00100000)
366#define BCSR4_DATA_VOICE ((uint)0x00080000)
367
368#define CONFIG_DRAM_40MHZ 1
369
370#ifdef CONFIG_MPC860T
371
372/* Interrupt level assignments.
373*/
374#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */
375
376#endif /* CONFIG_MPC860T */
377
378/* We don't use the 8259.
379*/
380#define NR_8259_INTS 0
381
wdenk0f8c9762002-08-19 11:57:05 +0000382/*
383 * MPC8xx CPM Options
384 */
385#define CONFIG_SCC_ENET 1
386#define CONFIG_SCC1_ENET 1
387#define CONFIG_FEC_ENET 1
388#undef CONFIG_CPM_IIC
389#undef CONFIG_UCODE_PATCH
390
391
392#define CONFIG_DISK_SPINUP_TIME 1000000
393
394
395/* PCMCIA configuration */
396
397#define PCMCIA_MAX_SLOTS 2
398
399#ifdef CONFIG_MPC860
400#define PCMCIA_SLOT_A 1
401#endif
402
403#endif /* __CONFIG_H */