blob: 8bf1616ecb485f1957e0ef776743cd69bb7c3a02 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Purna Chandra Mandal9ffa7a32016-01-28 15:30:15 +05302/*
3 * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
4 *
Purna Chandra Mandal9ffa7a32016-01-28 15:30:15 +05305 */
6
7#ifndef __MICROCHIP_DDR2_TIMING_H
8#define __MICROCHIP_DDR2_TIMING_H
9
10/* MPLL freq is 400MHz */
11#define T_CK 2500 /* 2500 psec */
12#define T_CK_CTRL (T_CK * 2)
13
14/* Burst length in cycles */
15#define BL 2
16/* default CAS latency for all speed grades */
17#define RL 5
18/* default write latency for all speed grades = CL-1 */
19#define WL 4
20
21/* From Micron MT47H64M16HR-3 data sheet */
22#define T_RFC_MIN 127500 /* psec */
23#define T_WR 15000 /* psec */
24#define T_RP 12500 /* psec */
25#define T_RCD 12500 /* psec */
26#define T_RRD 7500 /* psec */
27/* T_RRD_TCK is minimum of 2 clk periods, regardless of freq */
28#define T_RRD_TCK 2
29#define T_WTR 7500 /* psec */
30/* T_WTR_TCK is minimum of 2 clk periods, regardless of freq */
31#define T_WTR_TCK 2
32#define T_RTP 7500 /* psec */
33#define T_RTP_TCK (BL / 2)
34#define T_XP_TCK 2 /* clocks */
35#define T_CKE_TCK 3 /* clocks */
36#define T_XSNR (T_RFC_MIN + 10000) /* psec */
37#define T_DLLK 200 /* clocks */
38#define T_RAS_MIN 45000 /* psec */
39#define T_RC 57500 /* psec */
40#define T_FAW 35000 /* psec */
41#define T_MRD_TCK 2 /* clocks */
42#define T_RFI 7800000 /* psec */
43
44/* DDR Addressing */
45#define COL_BITS 10
46#define BA_BITS 3
47#define ROW_BITS 13
48#define CS_BITS 1
49
50/* DDR Addressing scheme: {CS, ROW, BA, COL} */
51#define COL_HI_RSHFT 0
52#define COL_HI_MASK 0
53#define COL_LO_MASK ((1 << COL_BITS) - 1)
54
55#define BA_RSHFT COL_BITS
56#define BA_MASK ((1 << BA_BITS) - 1)
57
58#define ROW_ADDR_RSHIFT (BA_RSHFT + BA_BITS)
59#define ROW_ADDR_MASK ((1 << ROW_BITS) - 1)
60
61#define CS_ADDR_RSHIFT 0
62#define CS_ADDR_MASK 0
63
64#endif /* __MICROCHIP_DDR2_TIMING_H */