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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +00002/*
3 * Bluewater Systems Snapper 9260 and 9G20 modules
4 *
5 * (C) Copyright 2011 Bluewater Systems
6 * Author: Andre Renaud <andre@bluewatersys.com>
7 * Author: Ryan Mallon <ryan@bluewatersys.com>
Ryan Mallonb8d41dd2011-06-05 07:21:22 +00008 */
9
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13/* SoC type is defined in boards.cfg */
14#include <asm/hardware.h>
Alexey Brodkin1ace4022014-02-26 17:47:58 +040015#include <linux/sizes.h>
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000016
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000017/* ARM asynchronous clock */
18#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
19#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000020
21/* CPU */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000022
23#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
24#define CONFIG_SETUP_MEMORY_TAGS
25#define CONFIG_INITRD_TAG
26#define CONFIG_SKIP_LOWLEVEL_INIT
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000027
28/* SDRAM */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000029#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
30#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
31#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
32 GENERATED_GBL_DATA_SIZE)
33
34/* Mem test settings */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000035
36/* NAND Flash */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000037#define CONFIG_SYS_MAX_NAND_DEVICE 1
38#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
39#define CONFIG_SYS_NAND_DBW_8
40#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
41#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
42#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
43#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
44
45/* Ethernet */
46#define CONFIG_MACB
47#define CONFIG_RMII
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000048#define CONFIG_NET_RETRY_COUNT 20
49#define CONFIG_RESET_PHY_R
Heiko Schocher4535a242013-11-18 08:07:23 +010050#define CONFIG_AT91_WANTS_COMMON_PHY
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000051#define CONFIG_TFTP_PORT
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000052
53/* USB */
54#define CONFIG_USB_ATMEL
Bo Shendcd2f1a2013-10-21 16:14:00 +080055#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000056#define CONFIG_USB_OHCI_NEW
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000057#define CONFIG_SYS_USB_OHCI_CPU_INIT
58#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
59#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
60#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000061
62/* GPIOs and IO expander */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000063#define CONFIG_ATMEL_LEGACY
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000064#define CONFIG_AT91_GPIO_PULLUP 1
65#define CONFIG_PCA953X
66#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
67#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
68
69/* UARTs/Serial console */
Simon Glass1a1927f2014-10-29 13:09:01 -060070#ifndef CONFIG_DM_SERIAL
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000071#define CONFIG_USART_BASE ATMEL_BASE_DBGU
72#define CONFIG_USART_ID ATMEL_ID_SYS
Simon Glass1a1927f2014-10-29 13:09:01 -060073#endif
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000074
75/* I2C - Bit-bashed */
Simon Glass69d9eda2021-07-10 21:14:32 -060076#define CONFIG_SYS_I2C_LEGACY
Heiko Schocherea818db2013-01-29 08:53:15 +010077#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
78#define CONFIG_SYS_I2C_SOFT_SPEED 100000
79#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000080#define CONFIG_SOFT_I2C_READ_REPEATED_START
Ryan Mallonb8d41dd2011-06-05 07:21:22 +000081#define I2C_INIT do { \
82 at91_set_gpio_output(AT91_PIN_PA23, 1); \
83 at91_set_gpio_output(AT91_PIN_PA24, 1); \
84 at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
85 at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
86 } while (0)
87#define I2C_SOFT_DECLARATIONS
88#define I2C_ACTIVE
89#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
90#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
91#define I2C_SDA(bit) do { \
92 if (bit) { \
93 at91_set_gpio_input(AT91_PIN_PA23, 1); \
94 } else { \
95 at91_set_gpio_output(AT91_PIN_PA23, 1); \
96 at91_set_gpio_value(AT91_PIN_PA23, bit); \
97 } \
98 } while (0)
99#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
100#define I2C_DELAY udelay(2)
101
102/* Boot options */
103#define CONFIG_SYS_LOAD_ADDR 0x23000000
Ryan Mallonb8d41dd2011-06-05 07:21:22 +0000104
105#define CONFIG_BOOTP_BOOTFILESIZE
Ryan Mallonb8d41dd2011-06-05 07:21:22 +0000106
107/* Environment settings */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +0000108
109/* Console settings */
Ryan Mallonb8d41dd2011-06-05 07:21:22 +0000110
111/* U-Boot memory settings */
112#define CONFIG_SYS_MALLOC_LEN (1 << 20)
Ryan Mallonb8d41dd2011-06-05 07:21:22 +0000113
Ryan Mallonb8d41dd2011-06-05 07:21:22 +0000114#endif /* __CONFIG_H */