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Wolfgang Grandeggercd12f612009-10-23 12:03:16 +02001/*
2 * (C) Copyright 2006
3 * MicroSys GmbH
4 *
5 * (C) Copyright 2009
6 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
7 *
8 * See file CREDITS for list of people who contributed to this
9 * project.
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 * MA 02111-1307 USA
25 */
26
27#ifndef __CONFIG_H
28#define __CONFIG_H
29
30/*
31 * High Level Configuration Options
32 */
33
34#define CONFIG_MPC5200
35#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
36#define CONFIG_MPX5200 1 /* ... on MPX5200 board */
37#define CONFIG_MPC5200_DDR 1 /* ... use DDR RAM */
38#define CONFIG_IPEK01 /* Motherboard is ipek01 */
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0xfc000000
41
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +020042#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
43
44#define CONFIG_MISC_INIT_R
45
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +020046#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
47#ifdef CONFIG_CMD_KGDB
48#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
49#endif
50
51/*
52 * Serial console configuration
53 */
54#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
55#define CONFIG_BAUDRATE 115200 /* ... at 9600 bps */
56#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
57
58#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
59
60/*
61 * Video configuration for LIME GDC
62 */
63#define CONFIG_VIDEO
64#ifdef CONFIG_VIDEO
65#define CONFIG_VIDEO_MB862xx
66#define CONFIG_VIDEO_MB862xx_ACCEL
67#define VIDEO_FB_16BPP_WORD_SWAP
68#define CONFIG_CFB_CONSOLE
69#define CONFIG_VIDEO_LOGO
70#define CONFIG_VIDEO_BMP_LOGO
71#define CONFIG_CONSOLE_EXTRA_INFO
72#define CONFIG_VGA_AS_SINGLE_DEVICE
73#define CONFIG_SYS_CONSOLE_IS_IN_ENV
74#define CONFIG_VIDEO_SW_CURSOR
75#define CONFIG_SPLASH_SCREEN
76#define CONFIG_VIDEO_BMP_GZIP
77#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20) /* decompressed img */
78/* Lime clock frequency */
79#define CONFIG_SYS_MB862xx_CCF 0x90000 /* geo 166MHz other 133MHz */
80/* SDRAM parameter */
81#define CONFIG_SYS_MB862xx_MMR 0x41c767e3
82#endif
83
84/*
85 * PCI Mapping:
86 * 0x40000000 - 0x4fffffff - PCI Memory
87 * 0x50000000 - 0x50ffffff - PCI IO Space
88 */
89#define CONFIG_PCI 1
90#define CONFIG_PCI_PNP 1
91#define CONFIG_PCI_SCAN_SHOW 1
92
93#define CONFIG_PCI_MEM_BUS 0x40000000
94#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
95#define CONFIG_PCI_MEM_SIZE 0x10000000
96
97#define CONFIG_PCI_IO_BUS 0x50000000
98#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
99#define CONFIG_PCI_IO_SIZE 0x01000000
100
101#define CONFIG_NET_MULTI 1
102#define CONFIG_MII 1
103#define CONFIG_EEPRO100 1
104#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
105
106/* Partitions */
107#define CONFIG_DOS_PARTITION
108
109/* USB */
110#define CONFIG_USB_OHCI_NEW
111#define CONFIG_SYS_OHCI_BE_CONTROLLER
112#define CONFIG_USB_STORAGE
113
114#define CONFIG_SYS_USB_OHCI_CPU_INIT
115#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
116#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
117#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
118
119/*
120 * Command line configuration.
121 */
122#include <config_cmd_default.h>
123
124#ifdef CONFIG_VIDEO
125#define CONFIG_CMD_BMP /* BMP support */
126#endif
127#define CONFIG_CMD_DATE /* support for RTC, date/time...*/
128#define CONFIG_CMD_DHCP /* DHCP Support */
129#define CONFIG_CMD_FAT /* FAT support */
130#define CONFIG_CMD_I2C /* I2C serial bus support */
131#define CONFIG_CMD_IDE /* IDE harddisk support */
132#define CONFIG_CMD_IRQ /* irqinfo */
133#define CONFIG_CMD_MII /* MII support */
134#define CONFIG_CMD_PCI /* pciinfo */
135#define CONFIG_CMD_USB /* USB Support */
136
137#define CONFIG_SYS_LOWBOOT 1
138
139/*
140 * Autobooting
141 */
142#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
143
144#define CONFIG_PREBOOT "echo;" \
145 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
146 "echo"
147
148#undef CONFIG_BOOTARGS
149
150#define CONFIG_EXTRA_ENV_SETTINGS \
151 "netdev=eth0\0" \
152 "consoledev=ttyPSC0\0" \
153 "hostname=ipek01\0" \
154 "nfsargs=setenv bootargs root=/dev/nfs rw " \
155 "nfsroot=${serverip}:${rootpath}\0" \
156 "ramargs=setenv bootargs root=/dev/ram rw\0" \
157 "addip=setenv bootargs ${bootargs} " \
158 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
159 ":${hostname}:${netdev}:off panic=1\0" \
160 "addtty=setenv bootargs ${bootargs} " \
161 "console=${consoledev},${baudrate}\0" \
162 "flash_nfs=run nfsargs addip addtty;" \
163 "bootm ${kernel_addr} - ${fdtaddr}\0" \
164 "flash_self=run ramargs addip addtty;" \
165 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
166 "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};" \
167 "run nfsargs addip addtty;" \
168 "bootm ${loadaddr} - ${fdtaddr}\0" \
169 "rootpath=/opt/eldk/ppc_6xx\0" \
170 "bootfile=ipek01/uImage\0" \
171 "load=tftp 100000 ipek01/u-boot.bin\0" \
172 "update=protect off FC000000 +60000; era FC000000 +60000; " \
173 "cp.b 100000 FC000000 ${filesize}\0" \
174 "upd=run load;run update\0" \
175 "fdtaddr=800000\0" \
176 "loadaddr=400000\0" \
177 "fdtfile=ipek01/ipek01.dtb\0" \
178 ""
179
180#define CONFIG_BOOTCOMMAND "run flash_self"
181
182/*
183 * IPB Bus clocking configuration.
184 */
185#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* for 133MHz */
186/* PCI clock must be 33, because board will not boot */
187#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for 66MHz */
188
189/*
190 * Open firmware flat tree support
191 */
192#define CONFIG_OF_LIBFDT 1
193#define CONFIG_OF_BOARD_SETUP 1
194
195#define OF_CPU "PowerPC,5200@0"
196#define OF_SOC "soc5200@f0000000"
197#define OF_TBCLK (bd->bi_busfreq / 4)
198
199/*
200 * I2C configuration
201 */
202#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
203#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
204
205#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
206#define CONFIG_SYS_I2C_SLAVE 0x7F
207
208/*
209 * EEPROM configuration
210 */
211#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
212#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
213#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
214#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
215
216/*
217 * RTC configuration
218 */
219#define CONFIG_RTC_PCF8563
220#define CONFIG_SYS_I2C_RTC_ADDR 0x51
221
222#define CONFIG_SYS_FLASH_BASE 0xFC000000
223#define CONFIG_SYS_FLASH_SIZE 0x01000000
224#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + \
225 CONFIG_SYS_MONITOR_LEN)
226
227#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
228#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */
229#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
230
231/* use CFI flash driver */
232#define CONFIG_FLASH_CFI_DRIVER
233#define CONFIG_SYS_FLASH_CFI
234#define CONFIG_SYS_FLASH_EMPTY_INFO
235#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
236
237/*
238 * Environment settings
239 */
240#define CONFIG_ENV_IS_IN_FLASH 1
241#define CONFIG_ENV_SIZE 0x10000
242#define CONFIG_ENV_SECT_SIZE 0x20000
243#define CONFIG_ENV_OVERWRITE 1
244#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
245#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
246
247/*
248 * Memory map
249 */
250#define CONFIG_SYS_MBAR 0xf0000000
251#define CONFIG_SYS_SDRAM_BASE 0x00000000
252#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
253#define CONFIG_SYS_SRAM_BASE 0xF1000000
254#define CONFIG_SYS_SRAM_SIZE 0x00200000
255#define CONFIG_SYS_LIME_BASE 0xE4000000
256#define CONFIG_SYS_LIME_SIZE 0x04000000
257#define CONFIG_SYS_FPGA_BASE 0xC0000000
258#define CONFIG_SYS_FPGA_SIZE 0x10000000
259#define CONFIG_SYS_MPEG_BASE 0xe2000000
260#define CONFIG_SYS_MPEG_SIZE 0x01000000
261#define CONFIG_SYS_CF_BASE 0xe1000000
262#define CONFIG_SYS_CF_SIZE 0x01000000
263
264/* Use SRAM until RAM will be available */
265#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
266/* End of used area in DPRAM */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200267#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200268
Wolfgang Denk553f0982010-10-26 13:32:32 +0200269#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200270 GENERATED_GBL_DATA_SIZE)
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200271#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
272
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200273#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200274#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
275# define CONFIG_SYS_RAMBOOT 1
276#endif
277
278#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */
279#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* Reserve 128 kB for malloc() */
280#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
281
282/*
283 * Ethernet configuration
284 */
285#define CONFIG_MPC5xxx_FEC 1
286#define CONFIG_MPC5xxx_FEC_MII100
287#define CONFIG_PHY_ADDR 0x00
288
289/*
290 * GPIO configuration
291 */
292#define CONFIG_SYS_GPS_PORT_CONFIG 0x1d556624
293
294/*
295 * Miscellaneous configurable options
296 */
297#define CONFIG_SYS_LONGHELP /* undef to save memory */
298#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
299#ifdef CONFIG_CMD_KGDB
300#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
301#else
302#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
303#endif
304/* Print Buffer Size */
305#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
306 sizeof(CONFIG_SYS_PROMPT) + 16)
307/* max number of command args */
308#define CONFIG_SYS_MAXARGS 16
309/* Boot Argument Buffer Size */
310#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
311
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200312#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
313#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1...15 MB in DRAM */
314
315#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
316
317#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
318#define CONFIG_LOOPW
319
320/*
321 * Various low-level settings
322 */
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200323#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
324#define CONFIG_SYS_HID0_FINAL HID0_ICE
Wolfgang Grandeggercd12f612009-10-23 12:03:16 +0200325
326#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
327#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
328#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
329#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
330#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
331#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
332#define CONFIG_SYS_CS3_START CONFIG_SYS_LIME_BASE
333#define CONFIG_SYS_CS3_SIZE CONFIG_SYS_LIME_SIZE
334#define CONFIG_SYS_CS6_START CONFIG_SYS_FPGA_BASE
335#define CONFIG_SYS_CS6_SIZE CONFIG_SYS_FPGA_SIZE
336#define CONFIG_SYS_CS5_START CONFIG_SYS_CF_BASE
337#define CONFIG_SYS_CS5_SIZE CONFIG_SYS_CF_SIZE
338#define CONFIG_SYS_CS7_START CONFIG_SYS_MPEG_BASE
339#define CONFIG_SYS_CS7_SIZE CONFIG_SYS_MPEG_SIZE
340
341#ifdef CONFIG_SYS_PCISPEED_66
342#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
343#define CONFIG_SYS_CS1_CFG 0x0004FB00
344#define CONFIG_SYS_CS2_CFG 0x0006F900
345#else
346#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
347#define CONFIG_SYS_CS1_CFG 0x0001FB00
348#define CONFIG_SYS_CS2_CFG 0x0002F90C
349#endif
350
351/*
352 * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
353 * waitstates, writeswap and readswap enabled
354 */
355#define CONFIG_SYS_CS3_CFG 0x00FFFB0C
356#define CONFIG_SYS_CS6_CFG 0x00FFFB0C
357#define CONFIG_SYS_CS7_CFG 0x4040751C
358
359#define CONFIG_SYS_CS_BURST 0x00000000
360#define CONFIG_SYS_CS_DEADCYCLE 0x33330000
361
362#define CONFIG_SYS_RESET_ADDRESS 0xff000000
363
364/*-----------------------------------------------------------------------
365 * USB stuff
366 *-----------------------------------------------------------------------
367 */
368#define CONFIG_USB_CLOCK 0x0001BBBB
369#define CONFIG_USB_CONFIG 0x00005000
370
371/*-----------------------------------------------------------------------
372 * IDE/ATA stuff Supports IDE harddisk
373 *-----------------------------------------------------------------------
374 */
375#define CONFIG_IDE_PREINIT
376
377#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
378#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
379
380#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
381
382#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
383
384/* Offset for data I/O */
385#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
386
387/* Offset for normal register accesses */
388#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
389
390/* Offset for alternate registers */
391#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
392
393/* Interval between registers */
394#define CONFIG_SYS_ATA_STRIDE 4
395
396#endif /* __CONFIG_H */