| Igal Liberman | 75ae51c | 2017-04-26 18:05:29 +0300 | [diff] [blame] | 1 | Marvell COMPHY SerDes lane bindings |
| 2 | ===================================== |
| 3 | |
| 4 | The COMPHY node includes a description of the COMPHY SerDes lane configuration. |
| 5 | The COMPHY driver initializes the MUX of the SerDes lanes, and powers up the SerDes |
| 6 | by dependencies on the FDT blob configurations |
| 7 | |
| 8 | Mandatory properties: |
| 9 | SoC specific: |
| 10 | - compatible: |
| 11 | The compatible should include "marvell,mvebu-comphy" |
| 12 | and the COMPHY per chip compatible: |
| 13 | "marvell,comphy-cp110" for CP110 available in Aramda70x0/80x0. |
| 14 | The COMPHY per chip used to set which MUX configuration to use, and COMPHY power-up revision. |
| 15 | - reg: Base address and size of the COMPHY and hpipe units. |
| 16 | - max-lanes: Maximum number of comphy lanes. |
| 17 | - mux-bitcount: Number of bits that are allocated for every MUX in the COMPHY-selector register. |
| 18 | Board specific: |
| 19 | - PHY: Entry that include the configuration of the PHY. |
| 20 | Every PHY should have the below parameters: |
| 21 | - phy-type: the mode of the PHY |
| 22 | Possible modes located in include/dt-bindings/comphy/comphy_data.h |
| 23 | Optional properties: |
| 24 | - phy-speed: the speed of the PHY |
| 25 | Possible speeds values located in include/dt-bindings/comphy/comphy_data.h |
| 26 | - phy-invert: Polarity invert (COMPHY_POLARITY_TXD_INVERT/COMPHY_POLARITY_RXD_INVERT) |
| 27 | the possible bits under include/dt-bindings/comphy/comphy_data.h |
| 28 | - clk-src: Set the clock source of PCIe, if configured to PCIe clock output |
| 29 | This relevant for SerDes lane 5 only (by default, lane 4 is the clock source) |
| 30 | for Armada-7040 boards. |
| 31 | - endpoint: Optional boolean specifying this SerDes should be configured as PCIe endpoint. |
| 32 | |
| 33 | Example: |
| 34 | cpm_comphy: comphy@441000 { |
| 35 | compatible = "marvell,mvebu-comphy", "marvell,comphy-cp110"; |
| 36 | reg = <0x441000 0x8>, <0x120000 0x8>; |
| 37 | mux-bitcount = <4>; |
| 38 | max-lanes = <6>; |
| 39 | |
| 40 | /* |
| 41 | * CP110 Serdes Configuration: |
| 42 | * Lane 0: SGMII1 |
| 43 | * Lane 1: SATA 0 |
| 44 | * Lane 2: USB HOST 0 |
| 45 | * Lane 3: SATA1 |
| 46 | * Lane 4: SFI (10G) |
| 47 | * Lane 5: SGMII2 |
| 48 | */ |
| 49 | phy0 { |
| 50 | phy-type = <COMPHY_TYPE_SGMII1>; |
| 51 | phy-speed = <COMPHY_SPEED_1_25G>; |
| 52 | }; |
| 53 | phy1 { |
| 54 | phy-type = <COMPHY_TYPE_SATA0>; |
| 55 | }; |
| 56 | phy2 { |
| 57 | phy-type = <COMPHY_TYPE_USB3_HOST0>; |
| 58 | }; |
| 59 | phy3 { |
| 60 | phy-type = <COMPHY_TYPE_SATA1>; |
| 61 | }; |
| 62 | phy4 { |
| 63 | phy-type = <COMPHY_TYPE_SFI>; |
| 64 | }; |
| 65 | phy5 { |
| 66 | phy-type = <COMPHY_TYPE_SGMII2>; |
| 67 | }; |
| 68 | }; |