blob: 6520f75c68b4f5158edd1d960dffa9fb64796e37 [file] [log] [blame]
Tirumala Marrid0e66652010-09-28 14:15:21 -07001/*
2 * Bluestone board support
3 *
4 * Copyright (c) 2010, Applied Micro Circuits Corporation
5 * Author: Tirumala R Marri <tmarri@apm.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Tirumala Marrid0e66652010-09-28 14:15:21 -07008 */
9
10#include <common.h>
11#include <asm/apm821xx.h>
12#include <libfdt.h>
13#include <fdt_support.h>
14#include <i2c.h>
15#include <asm/processor.h>
16#include <asm/io.h>
17#include <asm/mmu.h>
18#include <asm/ppc4xx-gpio.h>
19
20int board_early_init_f(void)
21{
22 /*
23 * Setup the interrupt controller polarities, triggers, etc.
24 */
25 mtdcr(UIC0SR, 0xffffffff); /* clear all */
26 mtdcr(UIC0ER, 0x00000000); /* disable all */
27 mtdcr(UIC0CR, 0x00000005); /* ATI & UIC1 crit are critical */
28 mtdcr(UIC0PR, 0xffffffff); /* per ref-board manual */
29 mtdcr(UIC0TR, 0x00000000); /* per ref-board manual */
30 mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */
31 mtdcr(UIC0SR, 0xffffffff); /* clear all */
32
33 mtdcr(UIC1SR, 0xffffffff); /* clear all */
34 mtdcr(UIC1ER, 0x00000000); /* disable all */
35 mtdcr(UIC1CR, 0x00000000); /* all non-critical */
36 mtdcr(UIC1PR, 0xffffffff); /* per ref-board manual */
37 mtdcr(UIC1TR, 0x00000000); /* per ref-board manual */
38 mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */
39 mtdcr(UIC1SR, 0xffffffff); /* clear all */
40
41 mtdcr(UIC2SR, 0xffffffff); /* clear all */
42 mtdcr(UIC2ER, 0x00000000); /* disable all */
43 mtdcr(UIC2CR, 0x00000000); /* all non-critical */
44 mtdcr(UIC2PR, 0xffffffff); /* per ref-board manual */
45 mtdcr(UIC2TR, 0x00000000); /* per ref-board manual */
46 mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */
47 mtdcr(UIC2SR, 0xffffffff); /* clear all */
48
49 mtdcr(UIC3SR, 0xffffffff); /* clear all */
50 mtdcr(UIC3ER, 0x00000000); /* disable all */
51 mtdcr(UIC3CR, 0x00000000); /* all non-critical */
52 mtdcr(UIC3PR, 0xffffffff); /* per ref-board manual */
53 mtdcr(UIC3TR, 0x00000000); /* per ref-board manual */
54 mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */
55 mtdcr(UIC3SR, 0xffffffff); /* clear all */
56
57 /*
58 * Configure PFC (Pin Function Control) registers
59 * UART0: 2 pins
60 */
61 mtsdr(SDR0_PFC1, 0x0000000);
62
63 return 0;
64}
65
66int checkboard(void)
67{
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000068 char buf[64];
69 int i = getenv_f("serial#", buf, sizeof(buf));
Tirumala Marrid0e66652010-09-28 14:15:21 -070070
71 puts("Board: Bluestone Evaluation Board");
72
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000073 if (i > 0) {
Tirumala Marrid0e66652010-09-28 14:15:21 -070074 puts(", serial# ");
Wolfgang Denkf0c0b3a2011-05-04 10:32:28 +000075 puts(buf);
Tirumala Marrid0e66652010-09-28 14:15:21 -070076 }
77 putc('\n');
78
79 return 0;
80}
81
82int misc_init_r(void)
83{
84 u32 sdr0_srst1 = 0;
85
86 /* Setup PLB4-AHB bridge based on the system address map */
87 mtdcr(AHB_TOP, 0x8000004B);
88 mtdcr(AHB_BOT, 0x8000004B);
89
90 /*
91 * The AHB Bridge core is held in reset after power-on or reset
92 * so enable it now
93 */
94 mfsdr(SDR0_SRST1, sdr0_srst1);
95 sdr0_srst1 &= ~SDR0_SRST1_AHB;
96 mtsdr(SDR0_SRST1, sdr0_srst1);
97
98 return 0;
99}