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wdenk5d3207d2002-08-21 22:08:56 +00001/*
Wolfgang Denk5b5eb9c2008-03-26 15:38:47 +01002 * (C) Copyright 2001-2008
wdenk5d3207d2002-08-21 22:08:56 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Keith Outwater, keith_outwater@mvis.com`
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25/*
26 * Date & Time support (no alarms) for Dallas Semiconductor (now Maxim)
27 * DS1337 Real Time Clock (RTC).
28 */
29
30#include <common.h>
31#include <command.h>
32#include <rtc.h>
33#include <i2c.h>
34
Michal Simek871c18d2008-07-14 19:45:37 +020035#if defined(CONFIG_CMD_DATE)
wdenk5d3207d2002-08-21 22:08:56 +000036
37/*---------------------------------------------------------------------*/
38#undef DEBUG_RTC
39
40#ifdef DEBUG_RTC
41#define DEBUGR(fmt,args...) printf(fmt ,##args)
42#else
43#define DEBUGR(fmt,args...)
44#endif
45/*---------------------------------------------------------------------*/
46
47/*
48 * RTC register addresses
49 */
50#define RTC_SEC_REG_ADDR 0x0
51#define RTC_MIN_REG_ADDR 0x1
52#define RTC_HR_REG_ADDR 0x2
53#define RTC_DAY_REG_ADDR 0x3
54#define RTC_DATE_REG_ADDR 0x4
55#define RTC_MON_REG_ADDR 0x5
56#define RTC_YR_REG_ADDR 0x6
57#define RTC_CTL_REG_ADDR 0x0e
58#define RTC_STAT_REG_ADDR 0x0f
Werner Pfisterb0078c82009-09-21 14:49:55 +020059#define RTC_TC_REG_ADDR 0x10
wdenk5d3207d2002-08-21 22:08:56 +000060
61/*
62 * RTC control register bits
63 */
Wolfgang Denk5b5eb9c2008-03-26 15:38:47 +010064#define RTC_CTL_BIT_A1IE 0x1 /* Alarm 1 interrupt enable */
65#define RTC_CTL_BIT_A2IE 0x2 /* Alarm 2 interrupt enable */
66#define RTC_CTL_BIT_INTCN 0x4 /* Interrupt control */
67#define RTC_CTL_BIT_RS1 0x8 /* Rate select 1 */
68#define RTC_CTL_BIT_RS2 0x10 /* Rate select 2 */
69#define RTC_CTL_BIT_DOSC 0x80 /* Disable Oscillator */
wdenk5d3207d2002-08-21 22:08:56 +000070
71/*
72 * RTC status register bits
73 */
Wolfgang Denk5b5eb9c2008-03-26 15:38:47 +010074#define RTC_STAT_BIT_A1F 0x1 /* Alarm 1 flag */
75#define RTC_STAT_BIT_A2F 0x2 /* Alarm 2 flag */
76#define RTC_STAT_BIT_OSF 0x80 /* Oscillator stop flag */
wdenk5d3207d2002-08-21 22:08:56 +000077
78
79static uchar rtc_read (uchar reg);
80static void rtc_write (uchar reg, uchar val);
wdenk5d3207d2002-08-21 22:08:56 +000081
82/*
83 * Get the current time from the RTC
84 */
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030085int rtc_get (struct rtc_time *tmp)
wdenk5d3207d2002-08-21 22:08:56 +000086{
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +030087 int rel = 0;
wdenk5d3207d2002-08-21 22:08:56 +000088 uchar sec, min, hour, mday, wday, mon_cent, year, control, status;
89
90 control = rtc_read (RTC_CTL_REG_ADDR);
91 status = rtc_read (RTC_STAT_REG_ADDR);
92 sec = rtc_read (RTC_SEC_REG_ADDR);
93 min = rtc_read (RTC_MIN_REG_ADDR);
94 hour = rtc_read (RTC_HR_REG_ADDR);
95 wday = rtc_read (RTC_DAY_REG_ADDR);
96 mday = rtc_read (RTC_DATE_REG_ADDR);
97 mon_cent = rtc_read (RTC_MON_REG_ADDR);
98 year = rtc_read (RTC_YR_REG_ADDR);
99
100 DEBUGR ("Get RTC year: %02x mon/cent: %02x mday: %02x wday: %02x "
101 "hr: %02x min: %02x sec: %02x control: %02x status: %02x\n",
102 year, mon_cent, mday, wday, hour, min, sec, control, status);
103
104 if (status & RTC_STAT_BIT_OSF) {
105 printf ("### Warning: RTC oscillator has stopped\n");
106 /* clear the OSF flag */
107 rtc_write (RTC_STAT_REG_ADDR,
108 rtc_read (RTC_STAT_REG_ADDR) & ~RTC_STAT_BIT_OSF);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300109 rel = -1;
wdenk5d3207d2002-08-21 22:08:56 +0000110 }
111
112 tmp->tm_sec = bcd2bin (sec & 0x7F);
113 tmp->tm_min = bcd2bin (min & 0x7F);
114 tmp->tm_hour = bcd2bin (hour & 0x3F);
115 tmp->tm_mday = bcd2bin (mday & 0x3F);
116 tmp->tm_mon = bcd2bin (mon_cent & 0x1F);
117 tmp->tm_year = bcd2bin (year) + ((mon_cent & 0x80) ? 2000 : 1900);
118 tmp->tm_wday = bcd2bin ((wday - 1) & 0x07);
119 tmp->tm_yday = 0;
120 tmp->tm_isdst= 0;
121
122 DEBUGR ("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
123 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
124 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
Yuri Tikhonovb73a19e2008-03-20 17:56:04 +0300125
126 return rel;
wdenk5d3207d2002-08-21 22:08:56 +0000127}
128
129
130/*
131 * Set the RTC
132 */
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200133int rtc_set (struct rtc_time *tmp)
wdenk5d3207d2002-08-21 22:08:56 +0000134{
135 uchar century;
136
137 DEBUGR ("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
138 tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday,
139 tmp->tm_hour, tmp->tm_min, tmp->tm_sec);
140
141 rtc_write (RTC_YR_REG_ADDR, bin2bcd (tmp->tm_year % 100));
142
143 century = (tmp->tm_year >= 2000) ? 0x80 : 0;
144 rtc_write (RTC_MON_REG_ADDR, bin2bcd (tmp->tm_mon) | century);
145
146 rtc_write (RTC_DAY_REG_ADDR, bin2bcd (tmp->tm_wday + 1));
147 rtc_write (RTC_DATE_REG_ADDR, bin2bcd (tmp->tm_mday));
148 rtc_write (RTC_HR_REG_ADDR, bin2bcd (tmp->tm_hour));
149 rtc_write (RTC_MIN_REG_ADDR, bin2bcd (tmp->tm_min));
150 rtc_write (RTC_SEC_REG_ADDR, bin2bcd (tmp->tm_sec));
Jean-Christophe PLAGNIOL-VILLARDd1e23192008-09-01 23:06:23 +0200151
152 return 0;
wdenk5d3207d2002-08-21 22:08:56 +0000153}
154
155
156/*
157 * Reset the RTC. We also enable the oscillator output on the
158 * SQW/INTB* pin and program it for 32,768 Hz output. Note that
159 * according to the datasheet, turning on the square wave output
160 * increases the current drain on the backup battery from about
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161 * 600 nA to 2uA. Define CONFIG_SYS_RTC_DS1337_NOOSC if you wish to turn
Joakim Tjernlundda8808d2008-03-26 13:02:13 +0100162 * off the OSC output.
wdenk5d3207d2002-08-21 22:08:56 +0000163 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#ifdef CONFIG_SYS_RTC_DS1337_NOOSC
Joakim Tjernlundda8808d2008-03-26 13:02:13 +0100165 #define RTC_DS1337_RESET_VAL \
Wolfgang Denk5b5eb9c2008-03-26 15:38:47 +0100166 (RTC_CTL_BIT_INTCN | RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
Joakim Tjernlundda8808d2008-03-26 13:02:13 +0100167#else
168 #define RTC_DS1337_RESET_VAL (RTC_CTL_BIT_RS1 | RTC_CTL_BIT_RS2)
169#endif
wdenk5d3207d2002-08-21 22:08:56 +0000170void rtc_reset (void)
171{
Joakim Tjernlundda8808d2008-03-26 13:02:13 +0100172 rtc_write (RTC_CTL_REG_ADDR, RTC_DS1337_RESET_VAL);
Werner Pfisterb0078c82009-09-21 14:49:55 +0200173#ifdef CONFIG_SYS_DS1339_TCR_VAL
174 rtc_write (RTC_TC_REG_ADDR, CONFIG_SYS_DS1339_TCR_VAL);
175#endif
wdenk5d3207d2002-08-21 22:08:56 +0000176}
177
178
179/*
180 * Helper functions
181 */
182
183static
184uchar rtc_read (uchar reg)
185{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186 return (i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, reg));
wdenk5d3207d2002-08-21 22:08:56 +0000187}
188
189
190static void rtc_write (uchar reg, uchar val)
191{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200192 i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, reg, val);
wdenk5d3207d2002-08-21 22:08:56 +0000193}
194
Jon Loeliger068b60a2007-07-10 10:27:39 -0500195#endif