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Wolfgang Denkad5bb452007-03-06 18:08:43 +01001/*
2 * (C) Copyright 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Wolfgang Denkad5bb452007-03-06 18:08:43 +01006 */
7
8#include <common.h>
9
10/*
11 * CPU test
12 * Ternary instructions instr rD,rA,rB
13 *
14 * Arithmetic instructions: add, addc, adde, subf, subfc, subfe,
15 * mullw, mulhw, mulhwu, divw, divwu
16 *
17 * The test contains a pre-built table of instructions, operands and
18 * expected results. For each table entry, the test will cyclically use
19 * different sets of operand registers and result registers.
20 */
21
Wolfgang Denkad5bb452007-03-06 18:08:43 +010022#include <post.h>
23#include "cpu_asm.h"
24
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025#if CONFIG_POST & CONFIG_SYS_POST_CPU
Wolfgang Denkad5bb452007-03-06 18:08:43 +010026
27extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1,
28 ulong op2);
29extern ulong cpu_post_makecr (long v);
30
31static struct cpu_post_three_s
32{
33 ulong cmd;
34 ulong op1;
35 ulong op2;
36 ulong res;
37} cpu_post_three_table[] =
38{
39 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020040 OP_ADD,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010041 100,
42 200,
43 300
44 },
45 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020046 OP_ADD,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010047 100,
48 -200,
49 -100
50 },
51 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020052 OP_ADDC,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010053 100,
54 200,
55 300
56 },
57 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020058 OP_ADDC,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010059 100,
60 -200,
61 -100
62 },
63 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020064 OP_ADDE,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010065 100,
66 200,
67 300
68 },
69 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020070 OP_ADDE,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010071 100,
72 -200,
73 -100
74 },
75 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020076 OP_SUBF,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010077 100,
78 200,
79 100
80 },
81 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020082 OP_SUBF,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010083 300,
84 200,
85 -100
86 },
87 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020088 OP_SUBFC,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010089 100,
90 200,
91 100
92 },
93 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +020094 OP_SUBFC,
Wolfgang Denkad5bb452007-03-06 18:08:43 +010095 300,
96 200,
97 -100
98 },
99 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200100 OP_SUBFE,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100101 100,
102 200,
103 200 + ~100
104 },
105 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200106 OP_SUBFE,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100107 300,
108 200,
109 200 + ~300
110 },
111 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200112 OP_MULLW,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100113 200,
114 300,
115 200 * 300
116 },
117 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200118 OP_MULHW,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100119 0x10000000,
120 0x10000000,
121 0x1000000
122 },
123 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200124 OP_MULHWU,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100125 0x80000000,
126 0x80000000,
127 0x40000000
128 },
129 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200130 OP_DIVW,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100131 -20,
132 5,
133 -4
134 },
135 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200136 OP_DIVWU,
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100137 0x8000,
138 0x200,
139 0x40
140 },
141};
Mike Frysingerd2397812011-05-10 07:28:35 +0000142static unsigned int cpu_post_three_size = ARRAY_SIZE(cpu_post_three_table);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100143
144int cpu_post_test_three (void)
145{
146 int ret = 0;
147 unsigned int i, reg;
148 int flag = disable_interrupts();
149
150 for (i = 0; i < cpu_post_three_size && ret == 0; i++)
151 {
152 struct cpu_post_three_s *test = cpu_post_three_table + i;
153
154 for (reg = 0; reg < 32 && ret == 0; reg++)
155 {
156 unsigned int reg0 = (reg + 0) % 32;
157 unsigned int reg1 = (reg + 1) % 32;
158 unsigned int reg2 = (reg + 2) % 32;
159 unsigned int stk = reg < 16 ? 31 : 15;
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200160 unsigned long code[] =
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100161 {
162 ASM_STW(stk, 1, -4),
163 ASM_ADDI(stk, 1, -24),
164 ASM_STW(3, stk, 12),
165 ASM_STW(4, stk, 16),
166 ASM_STW(reg0, stk, 8),
167 ASM_STW(reg1, stk, 4),
168 ASM_STW(reg2, stk, 0),
169 ASM_LWZ(reg1, stk, 12),
170 ASM_LWZ(reg0, stk, 16),
171 ASM_12(test->cmd, reg2, reg1, reg0),
172 ASM_STW(reg2, stk, 12),
173 ASM_LWZ(reg2, stk, 0),
174 ASM_LWZ(reg1, stk, 4),
175 ASM_LWZ(reg0, stk, 8),
176 ASM_LWZ(3, stk, 12),
177 ASM_ADDI(1, stk, 24),
178 ASM_LWZ(stk, 1, -4),
179 ASM_BLR,
180 };
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200181 unsigned long codecr[] =
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100182 {
183 ASM_STW(stk, 1, -4),
184 ASM_ADDI(stk, 1, -24),
185 ASM_STW(3, stk, 12),
186 ASM_STW(4, stk, 16),
187 ASM_STW(reg0, stk, 8),
188 ASM_STW(reg1, stk, 4),
189 ASM_STW(reg2, stk, 0),
190 ASM_LWZ(reg1, stk, 12),
191 ASM_LWZ(reg0, stk, 16),
192 ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C,
193 ASM_STW(reg2, stk, 12),
194 ASM_LWZ(reg2, stk, 0),
195 ASM_LWZ(reg1, stk, 4),
196 ASM_LWZ(reg0, stk, 8),
197 ASM_LWZ(3, stk, 12),
198 ASM_ADDI(1, stk, 24),
199 ASM_LWZ(stk, 1, -4),
200 ASM_BLR,
201 };
202 ulong res;
203 ulong cr;
204
205 if (ret == 0)
206 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200207 cr = 0;
208 cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100209
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200210 ret = res == test->res && cr == 0 ? 0 : -1;
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100211
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200212 if (ret != 0)
213 {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200214 post_log ("Error at three test %d !\n", i);
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200215 }
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100216 }
217
218 if (ret == 0)
219 {
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200220 cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2);
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100221
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200222 ret = res == test->res &&
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100223 (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
224
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200225 if (ret != 0)
226 {
Wolfgang Denk93e14592013-10-04 17:43:24 +0200227 post_log ("Error at three test %d !\n", i);
228 }
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100229 }
230 }
231 }
232
233 if (flag)
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200234 enable_interrupts();
Wolfgang Denkad5bb452007-03-06 18:08:43 +0100235
236 return ret;
237}
238
239#endif