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Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +01001/*
2 * Copyright (C) 2005-2006 Atmel Corporation
3 *
4 * Configuration settings for the ATSTK1002 CPU daughterboard
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +01007 */
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
Andreas Bießmann5d73bc72010-11-04 23:15:30 +000011#include <asm/arch/hardware.h>
Haavard Skinnemoena23e2772008-05-19 11:36:28 +020012
Andreas Bießmann09d623c2011-04-18 04:12:39 +000013#define CONFIG_AVR32
14#define CONFIG_AT32AP
15#define CONFIG_AT32AP7000
16#define CONFIG_ATSTK1006
17#define CONFIG_ATSTK1000
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010018
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010019
20/*
21 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
22 * frequency, the HSB and PBB at 1/2, and the PBA to run at 1/4 the
23 * PLL frequency.
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020024 * (CONFIG_SYS_OSC0_HZ * CONFIG_SYS_PLL0_MUL) / CONFIG_SYS_PLL0_DIV = PLL MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010025 */
Andreas Bießmann09d623c2011-04-18 04:12:39 +000026#define CONFIG_PLL
27#define CONFIG_SYS_POWER_MANAGER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020028#define CONFIG_SYS_OSC0_HZ 20000000
29#define CONFIG_SYS_PLL0_DIV 1
30#define CONFIG_SYS_PLL0_MUL 7
31#define CONFIG_SYS_PLL0_SUPPRESS_CYCLES 16
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010032/*
33 * Set the CPU running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020034 * PLL / (2^CONFIG_SYS_CLKDIV_CPU) = CPU MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010035 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020036#define CONFIG_SYS_CLKDIV_CPU 0
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010037/*
38 * Set the HSB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039 * PLL / (2^CONFIG_SYS_CLKDIV_HSB) = HSB MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010040 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041#define CONFIG_SYS_CLKDIV_HSB 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010042/*
43 * Set the PBA running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044 * PLL / (2^CONFIG_SYS_CLKDIV_PBA) = PBA MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010045 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020046#define CONFIG_SYS_CLKDIV_PBA 2
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010047/*
48 * Set the PBB running at:
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049 * PLL / (2^CONFIG_SYS_CLKDIV_PBB) = PBB MHz
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010050 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020051#define CONFIG_SYS_CLKDIV_PBB 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010052
Haavard Skinnemoen1f36f732010-08-12 13:52:54 +070053/* Reserve VM regions for SDRAM and NOR flash */
54#define CONFIG_SYS_NR_VM_REGIONS 2
55
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010056/*
57 * The PLLOPT register controls the PLL like this:
58 * icp = PLLOPT<2>
59 * ivco = PLLOPT<1:0>
60 *
61 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
62 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020063#define CONFIG_SYS_PLL0_OPT 0x04
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010064
Andreas Bießmannf4278b72010-11-04 23:15:31 +000065#define CONFIG_USART_BASE ATMEL_BASE_USART1
66#define CONFIG_USART_ID 1
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010067
68/* User serviceable stuff */
Andreas Bießmann09d623c2011-04-18 04:12:39 +000069#define CONFIG_DOS_PARTITION
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010070
Andreas Bießmann09d623c2011-04-18 04:12:39 +000071#define CONFIG_CMDLINE_TAG
72#define CONFIG_SETUP_MEMORY_TAGS
73#define CONFIG_INITRD_TAG
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010074
75#define CONFIG_STACKSIZE (2048)
76
77#define CONFIG_BAUDRATE 115200
78#define CONFIG_BOOTARGS \
79 "console=ttyS0 root=mtd3 fbmem=2400k"
80
81#define CONFIG_BOOTCOMMAND \
82 "fsload; bootm $(fileaddr)"
83
84/*
85 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
86 * data on the serial line may interrupt the boot sequence.
87 */
88#define CONFIG_BOOTDELAY 1
Andreas Bießmann09d623c2011-04-18 04:12:39 +000089#define CONFIG_AUTOBOOT
90#define CONFIG_AUTOBOOT_KEYED
Wolfgang Denkc37207d2008-07-16 16:38:59 +020091#define CONFIG_AUTOBOOT_PROMPT \
92 "Press SPACE to abort autoboot in %d seconds\n", bootdelay
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +010093#define CONFIG_AUTOBOOT_DELAY_STR "d"
94#define CONFIG_AUTOBOOT_STOP_STR " "
95
96/*
97 * After booting the board for the first time, new ethernet addresses
98 * should be generated and assigned to the environment variables
99 * "ethaddr" and "eth1addr". This is normally done during production.
100 */
Andreas Bießmann09d623c2011-04-18 04:12:39 +0000101#define CONFIG_OVERWRITE_ETHADDR_ONCE
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100102
103/*
104 * BOOTP options
105 */
106#define CONFIG_BOOTP_SUBNETMASK
107#define CONFIG_BOOTP_GATEWAY
108
109
110/*
111 * Command line configuration.
112 */
113#include <config_cmd_default.h>
114
115#define CONFIG_CMD_ASKENV
116#define CONFIG_CMD_DHCP
117#define CONFIG_CMD_EXT2
118#define CONFIG_CMD_FAT
119#define CONFIG_CMD_JFFS2
120#define CONFIG_CMD_MMC
121
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100122#undef CONFIG_CMD_FPGA
123#undef CONFIG_CMD_SETGETDCR
Wolfgang Denk74de7ae2009-04-01 23:34:12 +0200124#undef CONFIG_CMD_SOURCE
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100125#undef CONFIG_CMD_XIMG
126
Andreas Bießmann09d623c2011-04-18 04:12:39 +0000127#define CONFIG_ATMEL_USART
128#define CONFIG_MACB
129#define CONFIG_PORTMUX_PIO
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_NR_PIOS 5
Andreas Bießmann09d623c2011-04-18 04:12:39 +0000131#define CONFIG_SYS_HSDRAMC
132#define CONFIG_MMC
Sven Schnelle72fa4672011-10-21 14:49:25 +0200133#define CONFIG_GENERIC_ATMEL_MCI
134#define CONFIG_GENERIC_MMC
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100135
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_DCACHE_LINESZ 32
137#define CONFIG_SYS_ICACHE_LINESZ 32
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100138
139#define CONFIG_NR_DRAM_BANKS 1
140
Andreas Bießmann22178652011-06-28 04:15:58 +0000141#define CONFIG_SYS_FLASH_CFI
142#define CONFIG_FLASH_CFI_DRIVER
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_FLASH_BASE 0x00000000
145#define CONFIG_SYS_FLASH_SIZE 0x800000
146#define CONFIG_SYS_MAX_FLASH_BANKS 1
147#define CONFIG_SYS_MAX_FLASH_SECT 135
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
Andreas Bießmann47293c12011-04-18 04:12:44 +0000150#define CONFIG_SYS_TEXT_BASE 0x00000000
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_INTRAM_BASE INTERNAL_SRAM_BASE
153#define CONFIG_SYS_INTRAM_SIZE INTERNAL_SRAM_SIZE
154#define CONFIG_SYS_SDRAM_BASE EBI_SDRAM_BASE
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100155
Andreas Bießmann09d623c2011-04-18 04:12:39 +0000156#define CONFIG_ENV_IS_IN_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200157#define CONFIG_ENV_SIZE 65536
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE - CONFIG_ENV_SIZE)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100159
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INTRAM_BASE + CONFIG_SYS_INTRAM_SIZE)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100161
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_MALLOC_LEN (256*1024)
163#define CONFIG_SYS_DMA_ALLOC_LEN (16384)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100164
165/* Allow 4MB for the kernel run-time image */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200166#define CONFIG_SYS_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000)
167#define CONFIG_SYS_BOOTPARAMS_LEN (16 * 1024)
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100168
169/* Other configuration settings that shouldn't have to change all that often */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_PROMPT "U-Boot> "
171#define CONFIG_SYS_CBSIZE 256
172#define CONFIG_SYS_MAXARGS 16
173#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
Andreas Bießmann09d623c2011-04-18 04:12:39 +0000174#define CONFIG_SYS_LONGHELP
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_MEMTEST_START EBI_SDRAM_BASE
177#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x3f00000)
178#define CONFIG_SYS_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
Haavard Skinnemoen0a2e4872007-11-22 12:14:11 +0100179
180#endif /* __CONFIG_H */