Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 2 | /* |
| 3 | * Sysam stmark2 board configuration |
| 4 | * |
| 5 | * (C) Copyright 2017 Angelo Dureghello <angelo@sysam.it> |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 6 | */ |
| 7 | |
| 8 | #ifndef __STMARK2_CONFIG_H |
| 9 | #define __STMARK2_CONFIG_H |
| 10 | |
Mario Six | 5bc0543 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 11 | #define CONFIG_HOSTNAME "stmark2" |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 12 | |
| 13 | #define CONFIG_MCFUART |
| 14 | #define CONFIG_SYS_UART_PORT 0 |
| 15 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } |
| 16 | |
| 17 | #define LDS_BOARD_TEXT \ |
| 18 | board/sysam/stmark2/sbf_dram_init.o (.text*) |
| 19 | |
| 20 | #define CONFIG_TIMESTAMP |
| 21 | |
| 22 | #define CONFIG_BOOTARGS \ |
| 23 | "console=ttyS0,115200 root=/dev/ram0 rw " \ |
| 24 | "rootfstype=ramfs " \ |
| 25 | "rdinit=/bin/init " \ |
| 26 | "devtmpfs.mount=1" |
| 27 | |
| 28 | #define CONFIG_BOOTCOMMAND \ |
| 29 | "sf probe 0:1 50000000; " \ |
| 30 | "sf read ${loadaddr} 0x100000 ${kern_size}; " \ |
| 31 | "bootm ${loadaddr}" |
| 32 | |
| 33 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 34 | "kern_size=0x700000\0" \ |
| 35 | "loadaddr=0x40001000\0" \ |
| 36 | "-(rootfs)\0" \ |
| 37 | "update_uboot=loady ${loadaddr}; " \ |
| 38 | "sf probe 0:1 50000000; " \ |
| 39 | "sf erase 0 0x80000; " \ |
| 40 | "sf write ${loadaddr} 0 ${filesize}\0" \ |
| 41 | "update_kernel=loady ${loadaddr}; " \ |
| 42 | "setenv kern_size ${filesize}; saveenv; " \ |
| 43 | "sf probe 0:1 50000000; " \ |
| 44 | "sf erase 0x100000 0x700000; " \ |
| 45 | "sf write ${loadaddr} 0x100000 ${filesize}\0" \ |
| 46 | "update_rootfs=loady ${loadaddr}; " \ |
| 47 | "sf probe 0:1 50000000; " \ |
| 48 | "sf erase 0x00800000 0x100000; " \ |
| 49 | "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ |
| 50 | "" |
| 51 | |
| 52 | /* Realtime clock */ |
| 53 | #undef CONFIG_MCFRTC |
| 54 | #define CONFIG_RTC_MCFRRTC |
| 55 | #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 |
| 56 | |
| 57 | /* spi not partitions */ |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 58 | #define CONFIG_JFFS2_CMDLINE |
| 59 | #define CONFIG_JFFS2_DEV "nor0" |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 60 | |
| 61 | /* Timer */ |
| 62 | #define CONFIG_MCFTMR |
| 63 | #undef CONFIG_MCFPIT |
| 64 | |
| 65 | /* DSPI and Serial Flash */ |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 66 | #define CONFIG_CF_DSPI |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 67 | #define CONFIG_SERIAL_FLASH |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 68 | |
| 69 | #define CONFIG_SYS_SBFHDR_SIZE 0x7 |
| 70 | |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 71 | /* Input, PCI, Flexbus, and VCO */ |
| 72 | #define CONFIG_EXTRA_CLOCK |
| 73 | |
| 74 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 75 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 76 | |
| 77 | /* Print Buffer Size */ |
| 78 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 79 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 80 | #define CONFIG_SYS_MAXARGS 16 |
| 81 | /* Boot Argument Buffer Size */ |
| 82 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE |
| 83 | |
| 84 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) |
| 85 | #define CONFIG_SYS_MBAR 0xFC000000 |
| 86 | |
| 87 | /* |
| 88 | * Definitions for initial stack pointer and data area (in internal SRAM) |
| 89 | */ |
| 90 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
| 91 | /* End of used area in internal SRAM */ |
| 92 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 |
| 93 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
| 94 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ |
| 95 | GENERATED_GBL_DATA_SIZE) - 32) |
| 96 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 97 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) |
| 98 | |
| 99 | /* |
| 100 | * Start addresses for the final memory configuration |
| 101 | * (Set up by the startup code) |
| 102 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 103 | */ |
| 104 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| 105 | #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ |
| 106 | |
| 107 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) |
| 108 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) |
| 109 | #define CONFIG_SYS_DRAM_TEST |
| 110 | |
| 111 | #if defined(CONFIG_CF_SBF) |
| 112 | #define CONFIG_SERIAL_BOOT |
| 113 | #endif |
| 114 | |
| 115 | #if defined(CONFIG_SERIAL_BOOT) |
| 116 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
| 117 | #else |
| 118 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
| 119 | #endif |
| 120 | |
| 121 | #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) |
| 122 | /* Reserve 256 kB for Monitor */ |
| 123 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) |
| 124 | /* Reserve 256 kB for malloc() */ |
| 125 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) |
| 126 | |
| 127 | /* |
| 128 | * For booting Linux, the board info and command line data |
| 129 | * have to be in the first 8 MB of memory, since this is |
| 130 | * the maximum mapped by the Linux kernel during initialization ?? |
| 131 | */ |
| 132 | /* Initial Memory map for Linux */ |
| 133 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ |
| 134 | (CONFIG_SYS_SDRAM_SIZE << 20)) |
| 135 | |
| 136 | /* Configuration for environment |
| 137 | * Environment is embedded in u-boot in the second sector of the flash |
| 138 | */ |
| 139 | |
| 140 | #if defined(CONFIG_CF_SBF) |
| 141 | #define CONFIG_ENV_IS_IN_SPI_FLASH 1 |
Angelo Dureghello | a373024 | 2017-08-07 01:17:18 +0200 | [diff] [blame] | 142 | #define CONFIG_ENV_OFFSET 0x40000 |
| 143 | #define CONFIG_ENV_SIZE 0x2000 |
| 144 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
| 145 | #endif |
| 146 | |
| 147 | #undef CONFIG_ENV_OVERWRITE |
| 148 | |
| 149 | /* Cache Configuration */ |
| 150 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
| 151 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 152 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
| 153 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 154 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
| 155 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) |
| 156 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) |
| 157 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ |
| 158 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ |
| 159 | CF_ACR_EN | CF_ACR_SM_ALL) |
| 160 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ |
| 161 | CF_CACR_ICINVA | CF_CACR_EUSP) |
| 162 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ |
| 163 | CF_CACR_DEC | CF_CACR_DDCM_P | \ |
| 164 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) |
| 165 | |
| 166 | #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 167 | CONFIG_SYS_INIT_RAM_SIZE - 12) |
| 168 | |
| 169 | #endif /* __STMARK2_CONFIG_H */ |