blob: ad1a387cd2755548e4f695107e9d0ae817a0bad0 [file] [log] [blame]
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -04001/*
2 * Copyright 2013-2015 Arcturus Networks, Inc.
3 * http://www.arcturusnetworks.com/products/ucp1020/
4 * based on include/configs/p1_p2_rdb_pc.h
5 * original copyright follows:
6 * Copyright 2009-2011 Freescale Semiconductor, Inc.
7 *
8 * SPDX-License-Identifier: GPL-2.0+
9 */
10
11/*
12 * QorIQ uCP1020-xx boards configuration file
13 */
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040017#define CONFIG_FSL_ELBC
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040018#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
19#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */
20#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
21#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
22#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
23#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
24
25#if defined(CONFIG_TARTGET_UCP1020T1)
26
27#define CONFIG_UCP1020_REV_1_3
28
29#define CONFIG_BOARDNAME "uCP1020-64EE512-0U1-XR-T1"
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040030
31#define CONFIG_TSEC_ENET
32#define CONFIG_TSEC1
33#define CONFIG_TSEC3
34#define CONFIG_HAS_ETH0
35#define CONFIG_HAS_ETH1
36#define CONFIG_ETHADDR 00:19:D3:FF:FF:FF
37#define CONFIG_ETH1ADDR 00:19:D3:FF:FF:FE
38#define CONFIG_ETH2ADDR 00:19:D3:FF:FF:FD
39#define CONFIG_IPADDR 10.80.41.229
40#define CONFIG_SERVERIP 10.80.41.227
41#define CONFIG_NETMASK 255.255.252.0
42#define CONFIG_ETHPRIME "eTSEC3"
43
44#ifndef CONFIG_SPI_FLASH
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040045#endif
46#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
47
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040048#define CONFIG_SYS_L2_SIZE (256 << 10)
49
50#define CONFIG_LAST_STAGE_INIT
51
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040052#endif
53
54#if defined(CONFIG_TARGET_UCP1020)
55
56#define CONFIG_UCP1020
57#define CONFIG_UCP1020_REV_1_3
58
59#define CONFIG_BOARDNAME_LOCAL "uCP1020-64EEE512-OU1-XR"
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040060
61#define CONFIG_TSEC_ENET
62#define CONFIG_TSEC1
63#define CONFIG_TSEC2
64#define CONFIG_TSEC3
65#define CONFIG_HAS_ETH0
66#define CONFIG_HAS_ETH1
67#define CONFIG_HAS_ETH2
68#define CONFIG_ETHADDR 00:06:3B:FF:FF:FF
69#define CONFIG_ETH1ADDR 00:06:3B:FF:FF:FE
70#define CONFIG_ETH2ADDR 00:06:3B:FF:FF:FD
71#define CONFIG_IPADDR 192.168.1.81
72#define CONFIG_IPADDR1 192.168.1.82
73#define CONFIG_IPADDR2 192.168.1.83
74#define CONFIG_SERVERIP 192.168.1.80
75#define CONFIG_GATEWAYIP 102.168.1.1
76#define CONFIG_NETMASK 255.255.255.0
77#define CONFIG_ETHPRIME "eTSEC1"
78
79#ifndef CONFIG_SPI_FLASH
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040080#endif
81#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
82
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -040083#define CONFIG_SYS_L2_SIZE (256 << 10)
84
85#define CONFIG_LAST_STAGE_INIT
86
87#endif
88
89#ifdef CONFIG_SDCARD
90#define CONFIG_RAMBOOT_SDCARD
91#define CONFIG_SYS_RAMBOOT
92#define CONFIG_SYS_EXTRA_ENV_RELOC
93#define CONFIG_SYS_TEXT_BASE 0x11000000
94#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
95#endif
96
97#ifdef CONFIG_SPIFLASH
98#define CONFIG_RAMBOOT_SPIFLASH
99#define CONFIG_SYS_RAMBOOT
100#define CONFIG_SYS_EXTRA_ENV_RELOC
101#define CONFIG_SYS_TEXT_BASE 0x11000000
102#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
103#endif
104
105#ifndef CONFIG_SYS_TEXT_BASE
106#define CONFIG_SYS_TEXT_BASE 0xeff80000
107#endif
108#define CONFIG_SYS_TEXT_BASE_NOR 0xeff80000
109
110#ifndef CONFIG_RESET_VECTOR_ADDRESS
111#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
112#endif
113
114#ifndef CONFIG_SYS_MONITOR_BASE
115#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
116#endif
117
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400118#define CONFIG_MP
119
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400120#define CONFIG_ENV_OVERWRITE
121
122#define CONFIG_CMD_SATA
123#define CONFIG_SATA_SIL
124#define CONFIG_SYS_SATA_MAX_DEVICE 2
125#define CONFIG_LIBATA
126#define CONFIG_LBA48
127
128#define CONFIG_SYS_CLK_FREQ 66666666
129#define CONFIG_DDR_CLK_FREQ 66666666
130
131#define CONFIG_HWCONFIG
132
133#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
134#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
135#define CONFIG_DTT_SENSORS { 0, 1 } /* Sensor index */
136/*
137 * ADM1021/NCT72 temp sensor configuration (see dtt/adm1021.c for details).
138 * there will be one entry in this array for each two (dummy) sensors in
139 * CONFIG_DTT_SENSORS.
140 *
141 * For uCP1020 module:
142 * - only one ADM1021/NCT72
143 * - i2c addr 0x41
144 * - conversion rate 0x02 = 0.25 conversions/second
145 * - ALERT output disabled
146 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
147 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
148 */
149#define CONFIG_SYS_DTT_ADM1021 { { CONFIG_SYS_I2C_NCT72_ADDR, \
150 0x02, 0, 1, 0, 85, 1, 0, 85} }
151
152#define CONFIG_CMD_DTT
153
154/*
155 * These can be toggled for performance analysis, otherwise use default.
156 */
157#define CONFIG_L2_CACHE
158#define CONFIG_BTB
159
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400160#define CONFIG_ENABLE_36BIT_PHYS
161
162#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
163#define CONFIG_SYS_MEMTEST_END 0x1fffffff
164#define CONFIG_PANIC_HANG /* do not reset board on panic */
165
166#define CONFIG_SYS_CCSRBAR 0xffe00000
167#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
168
169/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
170 SPL code*/
171#ifdef CONFIG_SPL_BUILD
172#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
173#endif
174
175/* DDR Setup */
176#define CONFIG_DDR_ECC_ENABLE
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400177#ifndef CONFIG_DDR_ECC_ENABLE
178#define CONFIG_SYS_DDR_RAW_TIMING
179#define CONFIG_DDR_SPD
180#endif
181#define CONFIG_SYS_SPD_BUS_NUM 1
182#undef CONFIG_FSL_DDR_INTERACTIVE
183
184#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_512M
185#define CONFIG_CHIP_SELECTS_PER_CTRL 1
186#define CONFIG_SYS_SDRAM_SIZE (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
187#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
188#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
189
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400190#define CONFIG_DIMM_SLOTS_PER_CTLR 1
191
192/* Default settings for DDR3 */
193#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f
194#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302
195#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000
196#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007f
197#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014302
198#define CONFIG_SYS_DDR_CS1_CONFIG_2 0x00000000
199
200#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
201#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000
202#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000
203#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000
204
205#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
206#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8655A608
207#define CONFIG_SYS_DDR_SR_CNTR 0x00000000
208#define CONFIG_SYS_DDR_RCW_1 0x00000000
209#define CONFIG_SYS_DDR_RCW_2 0x00000000
210#ifdef CONFIG_DDR_ECC_ENABLE
211#define CONFIG_SYS_DDR_CONTROL 0xE70C0000 /* Type = DDR3 & ECC */
212#else
213#define CONFIG_SYS_DDR_CONTROL 0xC70C0000 /* Type = DDR3 */
214#endif
215#define CONFIG_SYS_DDR_CONTROL_2 0x04401050
216#define CONFIG_SYS_DDR_TIMING_4 0x00220001
217#define CONFIG_SYS_DDR_TIMING_5 0x03402400
218
219#define CONFIG_SYS_DDR_TIMING_3 0x00020000
220#define CONFIG_SYS_DDR_TIMING_0 0x00330004
221#define CONFIG_SYS_DDR_TIMING_1 0x6f6B4846
222#define CONFIG_SYS_DDR_TIMING_2 0x0FA8C8CF
223#define CONFIG_SYS_DDR_CLK_CTRL 0x03000000
224#define CONFIG_SYS_DDR_MODE_1 0x40461520
225#define CONFIG_SYS_DDR_MODE_2 0x8000c000
226#define CONFIG_SYS_DDR_INTERVAL 0x0C300000
227
228#undef CONFIG_CLOCKS_IN_MHZ
229
230/*
231 * Memory map
232 *
233 * 0x0000_0000 0x7fff_ffff DDR Up to 2GB cacheable
234 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable(PCIe * 2)
235 * 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
236 * 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 256K cacheable
237 * (early boot only)
238 * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
239 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
240 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
241 */
242
243/*
244 * Local Bus Definitions
245 */
246#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */
247#define CONFIG_SYS_FLASH_BASE 0xec000000
248
249#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
250
251#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
252 | BR_PS_16 | BR_V)
253
254#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
255
256#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
257#define CONFIG_SYS_FLASH_QUIET_TEST
258#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
259
260#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
261
262#undef CONFIG_SYS_FLASH_CHECKSUM
263#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
264#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
265
266#define CONFIG_FLASH_CFI_DRIVER
267#define CONFIG_SYS_FLASH_CFI
268#define CONFIG_SYS_FLASH_EMPTY_INFO
269#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
270
271#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
272
273#define CONFIG_SYS_INIT_RAM_LOCK
274#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */
275/* Initial L1 address */
276#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR
277#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
278#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
279/* Size of used area in RAM */
280#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
281
282#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
283 GENERATED_GBL_DATA_SIZE)
284#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
285
286#define CONFIG_SYS_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Mon */
287#define CONFIG_SYS_MALLOC_LEN (1024 * 1024)/* Reserved for malloc */
288
289#define CONFIG_SYS_PMC_BASE 0xff980000
290#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
291#define CONFIG_PMC_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_PMC_BASE_PHYS) | \
292 BR_PS_8 | BR_V)
293#define CONFIG_PMC_OR_PRELIM (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
294 OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
295 OR_GPCM_EAD)
296
297#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
298#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
299#ifdef CONFIG_NAND_FSL_ELBC
300#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
301#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
302#endif
303
304/* Serial Port - controlled on board with jumper J8
305 * open - index 2
306 * shorted - index 1
307 */
308#define CONFIG_CONS_INDEX 1
309#undef CONFIG_SERIAL_SOFTWARE_FIFO
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400310#define CONFIG_SYS_NS16550_SERIAL
311#define CONFIG_SYS_NS16550_REG_SIZE 1
312#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
313#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
314#define CONFIG_NS16550_MIN_FUNCTIONS
315#endif
316
317#define CONFIG_SYS_BAUDRATE_TABLE \
318 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
319
320#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
321#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
322
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400323/* I2C */
324#define CONFIG_SYS_I2C
325#define CONFIG_SYS_I2C_FSL
326#define CONFIG_SYS_FSL_I2C_SPEED 400000
327#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
328#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
329#define CONFIG_SYS_FSL_I2C2_SPEED 400000
330#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
331#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
332#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
333#define CONFIG_SYS_SPD_BUS_NUM 1 /* For rom_loc and flash bank */
334
335#define CONFIG_RTC_DS1337
336#define CONFIG_SYS_RTC_DS1337_NOOSC
337#define CONFIG_SYS_I2C_RTC_ADDR 0x68
338#define CONFIG_SYS_I2C_PCA9557_ADDR 0x18
339#define CONFIG_SYS_I2C_NCT72_ADDR 0x4C
340#define CONFIG_SYS_I2C_IDT6V49205B 0x69
341
342/*
343 * eSPI - Enhanced SPI
344 */
345#define CONFIG_HARD_SPI
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400346
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400347#define CONFIG_SF_DEFAULT_SPEED 10000000
348#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
349
350#if defined(CONFIG_PCI)
351/*
352 * General PCI
353 * Memory space is mapped 1-1, but I/O space must start from 0.
354 */
355
356/* controller 2, direct to uli, tgtid 2, Base address 9000 */
357#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT CON9"
358#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
359#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
360#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
361#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
362#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
363#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
364#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
365#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
366
367/* controller 1, Slot 2, tgtid 1, Base address a000 */
368#define CONFIG_SYS_PCIE1_NAME "PCIe SLOT CON10"
369#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
370#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
371#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000
372#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
373#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000
374#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
375#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000
376#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
377
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400378#define CONFIG_CMD_PCI
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400379
380#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400381#endif /* CONFIG_PCI */
382
383/*
384 * Environment
385 */
386#ifdef CONFIG_ENV_FIT_UCBOOT
387
388#define CONFIG_ENV_IS_IN_FLASH
389#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x20000)
390#define CONFIG_ENV_SIZE 0x20000
391#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
392
393#else
394
395#define CONFIG_ENV_SPI_BUS 0
396#define CONFIG_ENV_SPI_CS 0
397#define CONFIG_ENV_SPI_MAX_HZ 10000000
398#define CONFIG_ENV_SPI_MODE 0
399
400#ifdef CONFIG_RAMBOOT_SPIFLASH
401
402#define CONFIG_ENV_IS_IN_SPI_FLASH
403#define CONFIG_ENV_SIZE 0x3000 /* 12KB */
404#define CONFIG_ENV_OFFSET 0x2000 /* 8KB */
405#define CONFIG_ENV_SECT_SIZE 0x1000
406
407#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
408/* Address and size of Redundant Environment Sector */
409#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
410#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
411#endif
412
413#elif defined(CONFIG_RAMBOOT_SDCARD)
414#define CONFIG_ENV_IS_IN_MMC
415#define CONFIG_FSL_FIXED_MMC_LOCATION
416#define CONFIG_ENV_SIZE 0x2000
417#define CONFIG_SYS_MMC_ENV_DEV 0
418
419#elif defined(CONFIG_SYS_RAMBOOT)
420#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
421#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
422#define CONFIG_ENV_SIZE 0x2000
423
424#else
425#define CONFIG_ENV_IS_IN_FLASH
426#define CONFIG_ENV_BASE (CONFIG_SYS_FLASH_BASE)
427#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
428#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
429#define CONFIG_ENV_ADDR (CONFIG_ENV_BASE + 0xC0000)
430#if defined(CONFIG_SYS_REDUNDAND_ENVIRONMENT)
431/* Address and size of Redundant Environment Sector */
432#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
433#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
434#endif
435
436#endif
437
438#endif /* CONFIG_ENV_FIT_UCBOOT */
439
440#define CONFIG_LOADS_ECHO /* echo on for serial download */
441#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
442
443/*
444 * Command line configuration.
445 */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400446#define CONFIG_CMD_IRQ
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400447#define CONFIG_CMD_DATE
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400448#define CONFIG_CMD_IRQ
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400449#define CONFIG_CMD_REGINFO
450#define CONFIG_CMD_ERRATA
451#define CONFIG_CMD_CRAMFS
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400452
453/*
454 * USB
455 */
456#define CONFIG_HAS_FSL_DR_USB
457
458#if defined(CONFIG_HAS_FSL_DR_USB)
459#define CONFIG_USB_EHCI
460
461#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
462
463#ifdef CONFIG_USB_EHCI
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400464#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
465#define CONFIG_USB_EHCI_FSL
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400466#endif
467#endif
468
469#undef CONFIG_WATCHDOG /* watchdog disabled */
470
471#ifdef CONFIG_MMC
472#define CONFIG_FSL_ESDHC
473#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400474#define CONFIG_MMC_SPI
475#define CONFIG_CMD_MMC_SPI
476#define CONFIG_GENERIC_MMC
477#endif
478
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400479/* Misc Extra Settings */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400480#undef CONFIG_WATCHDOG /* watchdog disabled */
481
482/*
483 * Miscellaneous configurable options
484 */
485#define CONFIG_SYS_LONGHELP /* undef to save memory */
486#define CONFIG_CMDLINE_EDITING /* Command-line editing */
487#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400488#if defined(CONFIG_CMD_KGDB)
489#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
490#else
491#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
492#endif
493#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
494 /* Print Buffer Size */
495#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
496#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
497#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms tick */
498
499/*
500 * For booting Linux, the board info and command line data
501 * have to be in the first 64 MB of memory, since this is
502 * the maximum mapped by the Linux kernel during initialization.
503 */
504#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux*/
505#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
506
507#if defined(CONFIG_CMD_KGDB)
508#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
509#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
510#endif
511
512/*
513 * Environment Configuration
514 */
515
516#if defined(CONFIG_TSEC_ENET)
517
518#if defined(CONFIG_UCP1020_REV_1_2)
519#define CONFIG_PHY_MICREL_KSZ9021
520#elif defined(CONFIG_UCP1020_REV_1_3)
521#define CONFIG_PHY_MICREL_KSZ9031
522#else
523#error "UCP1020 module revision is not defined !!!"
524#endif
525
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400526#define CONFIG_BOOTP_SERVERIP
527
528#define CONFIG_MII /* MII PHY management */
529#define CONFIG_TSEC1_NAME "eTSEC1"
530#define CONFIG_TSEC2_NAME "eTSEC2"
531#define CONFIG_TSEC3_NAME "eTSEC3"
532
533#define TSEC1_PHY_ADDR 4
534#define TSEC2_PHY_ADDR 0
535#define TSEC2_PHY_ADDR_SGMII 0x00
536#define TSEC3_PHY_ADDR 6
537
538#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
539#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
540#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
541
542#define TSEC1_PHYIDX 0
543#define TSEC2_PHYIDX 0
544#define TSEC3_PHYIDX 0
545
546#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
547
548#endif
549
550#define CONFIG_HOSTNAME UCP1020
551#define CONFIG_ROOTPATH "/opt/nfsroot"
552#define CONFIG_BOOTFILE "uImage"
553#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
554
555/* default location for tftp and bootm */
556#define CONFIG_LOADADDR 1000000
557
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400558#define CONFIG_BOOTARGS /* the boot command will set bootargs */
559
560#define CONFIG_BAUDRATE 115200
561
562#if defined(CONFIG_DONGLE)
563
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400564#define CONFIG_EXTRA_ENV_SETTINGS \
565"bootcmd=run prog_spi_mbrbootcramfs\0" \
566"bootfile=uImage\0" \
567"consoledev=ttyS0\0" \
568"cramfsfile=image.cramfs\0" \
569"dtbaddr=0x00c00000\0" \
570"dtbfile=image.dtb\0" \
571"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
572"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
573"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
574"fileaddr=0x01000000\0" \
575"filesize=0x00080000\0" \
576"flashmbr=sf probe 0; " \
577 "tftp $loadaddr $mbr; " \
578 "sf erase $mbr_offset +$filesize; " \
579 "sf write $loadaddr $mbr_offset $filesize\0" \
580"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
581 "protect off $nor_recoveryaddr +$filesize; " \
582 "erase $nor_recoveryaddr +$filesize; " \
583 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
584 "protect on $nor_recoveryaddr +$filesize\0 " \
585"flashuboot=tftp $ubootaddr $ubootfile; " \
586 "protect off $nor_ubootaddr +$filesize; " \
587 "erase $nor_ubootaddr +$filesize; " \
588 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
589 "protect on $nor_ubootaddr +$filesize\0 " \
590"flashworking=tftp $workingaddr $cramfsfile; " \
591 "protect off $nor_workingaddr +$filesize; " \
592 "erase $nor_workingaddr +$filesize; " \
593 "cp.b $workingaddr $nor_workingaddr $filesize; " \
594 "protect on $nor_workingaddr +$filesize\0 " \
595"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
596"kerneladdr=0x01100000\0" \
597"kernelfile=uImage\0" \
598"loadaddr=0x01000000\0" \
599"mbr=uCP1020d.mbr\0" \
600"mbr_offset=0x00000000\0" \
601"mmbr=uCP1020Quiet.mbr\0" \
602"mmcpart=0:2\0" \
603"mmc__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
604 "mmc erase 1 1; " \
605 "mmc write $loadaddr 1 1\0" \
606"mmc__uboot=fatload mmc $mmcpart $loadaddr $ubootfile; " \
607 "mmc erase 0x40 0x400; " \
608 "mmc write $loadaddr 0x40 0x400\0" \
609"netdev=eth0\0" \
610"nor_recoveryaddr=0xEC0A0000\0" \
611"nor_ubootaddr=0xEFF80000\0" \
612"nor_workingaddr=0xECFA0000\0" \
613"norbootrecovery=setenv bootargs $recoverybootargs" \
614 " console=$consoledev,$baudrate $othbootargs; " \
615 "run norloadrecovery; " \
616 "bootm $kerneladdr - $dtbaddr\0" \
617"norbootworking=setenv bootargs $workingbootargs" \
618 " console=$consoledev,$baudrate $othbootargs; " \
619 "run norloadworking; " \
620 "bootm $kerneladdr - $dtbaddr\0" \
621"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
622 "setenv cramfsaddr $nor_recoveryaddr; " \
623 "cramfsload $dtbaddr $dtbfile; " \
624 "cramfsload $kerneladdr $kernelfile\0" \
625"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
626 "setenv cramfsaddr $nor_workingaddr; " \
627 "cramfsload $dtbaddr $dtbfile; " \
628 "cramfsload $kerneladdr $kernelfile\0" \
629"prog_spi_mbr=run spi__mbr\0" \
630"prog_spi_mbrboot=run spi__mbr; run spi__boot1; run spi__boot2\0" \
631"prog_spi_mbrbootcramfs=run spi__mbr; run spi__boot1; run spi__boot2; " \
632 "run spi__cramfs\0" \
633"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
634 " console=$consoledev,$baudrate $othbootargs; " \
635 "tftp $rootfsaddr $rootfsfile; " \
636 "tftp $loadaddr $kernelfile; " \
637 "tftp $dtbaddr $dtbfile; " \
638 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
639"ramdisk_size=120000\0" \
640"ramdiskfile=rootfs.ext2.gz.uboot\0" \
641"recoveryaddr=0x02F00000\0" \
642"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
643"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
644 "mw.l 0xffe0f008 0x00400000\0" \
645"rootfsaddr=0x02F00000\0" \
646"rootfsfile=rootfs.ext2.gz.uboot\0" \
647"rootpath=/opt/nfsroot\0" \
648"spi__boot1=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
649 "protect off 0xeC000000 +$filesize; " \
650 "erase 0xEC000000 +$filesize; " \
651 "cp.b $loadaddr 0xEC000000 $filesize; " \
652 "cmp.b $loadaddr 0xEC000000 $filesize; " \
653 "protect on 0xeC000000 +$filesize\0" \
654"spi__boot2=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
655 "protect off 0xeFF80000 +$filesize; " \
656 "erase 0xEFF80000 +$filesize; " \
657 "cp.b $loadaddr 0xEFF80000 $filesize; " \
658 "cmp.b $loadaddr 0xEFF80000 $filesize; " \
659 "protect on 0xeFF80000 +$filesize\0" \
660"spi__bootd=fatload mmc $mmcpart $loadaddr $ubootd; " \
661 "sf probe 0; sf erase 0x8000 +$filesize; " \
662 "sf write $loadaddr 0x8000 $filesize\0" \
663"spi__cramfs=fatload mmc $mmcpart $loadaddr image.cramfs; " \
664 "protect off 0xec0a0000 +$filesize; " \
665 "erase 0xeC0A0000 +$filesize; " \
666 "cp.b $loadaddr 0xeC0A0000 $filesize; " \
667 "protect on 0xec0a0000 +$filesize\0" \
668"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
669 "sf probe 1; sf erase 0 +$filesize; " \
670 "sf write $loadaddr 0 $filesize\0" \
671"spi__mbrd=fatload mmc $mmcpart $loadaddr $mbr; " \
672 "sf probe 0; sf erase 0 +$filesize; " \
673 "sf write $loadaddr 0 $filesize\0" \
674"tftpflash=tftpboot $loadaddr $uboot; " \
675 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
676 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
677 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
678 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
679 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
680"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
681"ubootaddr=0x01000000\0" \
682"ubootfile=u-boot.bin\0" \
683"ubootd=u-boot4dongle.bin\0" \
684"upgrade=run flashworking\0" \
685"usb_phy_type=ulpi\0 " \
686"workingaddr=0x02F00000\0" \
687"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
688
689#else
690
691#if defined(CONFIG_UCP1020T1)
692
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400693#define CONFIG_EXTRA_ENV_SETTINGS \
694"bootcmd=run releasefpga; run norbootworking || run norbootrecovery\0" \
695"bootfile=uImage\0" \
696"consoledev=ttyS0\0" \
697"cramfsfile=image.cramfs\0" \
698"dtbaddr=0x00c00000\0" \
699"dtbfile=image.dtb\0" \
700"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
701"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
702"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
703"fileaddr=0x01000000\0" \
704"filesize=0x00080000\0" \
705"flashmbr=sf probe 0; " \
706 "tftp $loadaddr $mbr; " \
707 "sf erase $mbr_offset +$filesize; " \
708 "sf write $loadaddr $mbr_offset $filesize\0" \
709"flashrecovery=tftp $recoveryaddr $cramfsfile; " \
710 "protect off $nor_recoveryaddr +$filesize; " \
711 "erase $nor_recoveryaddr +$filesize; " \
712 "cp.b $recoveryaddr $nor_recoveryaddr $filesize; " \
713 "protect on $nor_recoveryaddr +$filesize\0 " \
714"flashuboot=tftp $ubootaddr $ubootfile; " \
715 "protect off $nor_ubootaddr +$filesize; " \
716 "erase $nor_ubootaddr +$filesize; " \
717 "cp.b $ubootaddr $nor_ubootaddr $filesize; " \
718 "protect on $nor_ubootaddr +$filesize\0 " \
719"flashworking=tftp $workingaddr $cramfsfile; " \
720 "protect off $nor_workingaddr +$filesize; " \
721 "erase $nor_workingaddr +$filesize; " \
722 "cp.b $workingaddr $nor_workingaddr $filesize; " \
723 "protect on $nor_workingaddr +$filesize\0 " \
724"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
725"kerneladdr=0x01100000\0" \
726"kernelfile=uImage\0" \
727"loadaddr=0x01000000\0" \
728"mbr=uCP1020.mbr\0" \
729"mbr_offset=0x00000000\0" \
730"netdev=eth0\0" \
731"nor_recoveryaddr=0xEC0A0000\0" \
732"nor_ubootaddr=0xEFF80000\0" \
733"nor_workingaddr=0xECFA0000\0" \
734"norbootrecovery=setenv bootargs $recoverybootargs" \
735 " console=$consoledev,$baudrate $othbootargs; " \
736 "run norloadrecovery; " \
737 "bootm $kerneladdr - $dtbaddr\0" \
738"norbootworking=setenv bootargs $workingbootargs" \
739 " console=$consoledev,$baudrate $othbootargs; " \
740 "run norloadworking; " \
741 "bootm $kerneladdr - $dtbaddr\0" \
742"norloadrecovery=mw.l $kerneladdr 0x0 0x00a00000; " \
743 "setenv cramfsaddr $nor_recoveryaddr; " \
744 "cramfsload $dtbaddr $dtbfile; " \
745 "cramfsload $kerneladdr $kernelfile\0" \
746"norloadworking=mw.l $kerneladdr 0x0 0x00a00000; " \
747 "setenv cramfsaddr $nor_workingaddr; " \
748 "cramfsload $dtbaddr $dtbfile; " \
749 "cramfsload $kerneladdr $kernelfile\0" \
750"othbootargs=quiet\0" \
751"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
752 " console=$consoledev,$baudrate $othbootargs; " \
753 "tftp $rootfsaddr $rootfsfile; " \
754 "tftp $loadaddr $kernelfile; " \
755 "tftp $dtbaddr $dtbfile; " \
756 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
757"ramdisk_size=120000\0" \
758"ramdiskfile=rootfs.ext2.gz.uboot\0" \
759"recoveryaddr=0x02F00000\0" \
760"recoverybootargs=root=/dev/mtdblock0 rootfstype=cramfs ro\0" \
761"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
762 "mw.l 0xffe0f008 0x00400000\0" \
763"rootfsaddr=0x02F00000\0" \
764"rootfsfile=rootfs.ext2.gz.uboot\0" \
765"rootpath=/opt/nfsroot\0" \
766"silent=1\0" \
767"tftpflash=tftpboot $loadaddr $uboot; " \
768 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
769 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
770 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
771 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
772 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
773"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
774"ubootaddr=0x01000000\0" \
775"ubootfile=u-boot.bin\0" \
776"upgrade=run flashworking\0" \
777"workingaddr=0x02F00000\0" \
778"workingbootargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0"
779
780#else /* For Arcturus Modules */
781
Oleksandr G Zhadan8b0044f2015-04-29 16:57:39 -0400782#define CONFIG_EXTRA_ENV_SETTINGS \
783"bootcmd=run norkernel\0" \
784"bootfile=uImage\0" \
785"consoledev=ttyS0\0" \
786"dtbaddr=0x00c00000\0" \
787"dtbfile=image.dtb\0" \
788"ethaddr=" __stringify(CONFIG_ETHADDR) "\0" \
789"eth1addr=" __stringify(CONFIG_ETH1ADDR) "\0" \
790"eth2addr=" __stringify(CONFIG_ETH2ADDR) "\0" \
791"fileaddr=0x01000000\0" \
792"filesize=0x00080000\0" \
793"flashmbr=sf probe 0; " \
794 "tftp $loadaddr $mbr; " \
795 "sf erase $mbr_offset +$filesize; " \
796 "sf write $loadaddr $mbr_offset $filesize\0" \
797"flashuboot=tftp $loadaddr $ubootfile; " \
798 "protect off $nor_ubootaddr0 +$filesize; " \
799 "erase $nor_ubootaddr0 +$filesize; " \
800 "cp.b $loadaddr $nor_ubootaddr0 $filesize; " \
801 "protect on $nor_ubootaddr0 +$filesize; " \
802 "protect off $nor_ubootaddr1 +$filesize; " \
803 "erase $nor_ubootaddr1 +$filesize; " \
804 "cp.b $loadaddr $nor_ubootaddr1 $filesize; " \
805 "protect on $nor_ubootaddr1 +$filesize\0 " \
806"format0=protect off $part0base +$part0size; " \
807 "erase $part0base +$part0size\0" \
808"format1=protect off $part1base +$part1size; " \
809 "erase $part1base +$part1size\0" \
810"format2=protect off $part2base +$part2size; " \
811 "erase $part2base +$part2size\0" \
812"format3=protect off $part3base +$part3size; " \
813 "erase $part3base +$part3size\0" \
814"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0 " \
815"kerneladdr=0x01100000\0" \
816"kernelargs=root=/dev/mtdblock1 rootfstype=cramfs ro\0" \
817"kernelfile=uImage\0" \
818"loadaddr=0x01000000\0" \
819"mbr=uCP1020.mbr\0" \
820"mbr_offset=0x00000000\0" \
821"netdev=eth0\0" \
822"nor_ubootaddr0=0xEC000000\0" \
823"nor_ubootaddr1=0xEFF80000\0" \
824"norkernel=setenv bootargs $kernelargs console=$consoledev,$baudrate; " \
825 "run norkernelload; " \
826 "bootm $kerneladdr - $dtbaddr\0" \
827"norkernelload=mw.l $kerneladdr 0x0 0x00a00000; " \
828 "setenv cramfsaddr $part0base; " \
829 "cramfsload $dtbaddr $dtbfile; " \
830 "cramfsload $kerneladdr $kernelfile\0" \
831"part0base=0xEC100000\0" \
832"part0size=0x00700000\0" \
833"part1base=0xEC800000\0" \
834"part1size=0x02000000\0" \
835"part2base=0xEE800000\0" \
836"part2size=0x00800000\0" \
837"part3base=0xEF000000\0" \
838"part3size=0x00F80000\0" \
839"partENVbase=0xEC080000\0" \
840"partENVsize=0x00080000\0" \
841"program0=tftp part0-000000.bin; " \
842 "protect off $part0base +$filesize; " \
843 "erase $part0base +$filesize; " \
844 "cp.b $loadaddr $part0base $filesize; " \
845 "echo Verifying...; " \
846 "cmp.b $loadaddr $part0base $filesize\0" \
847"program1=tftp part1-000000.bin; " \
848 "protect off $part1base +$filesize; " \
849 "erase $part1base +$filesize; " \
850 "cp.b $loadaddr $part1base $filesize; " \
851 "echo Verifying...; " \
852 "cmp.b $loadaddr $part1base $filesize\0" \
853"program2=tftp part2-000000.bin; " \
854 "protect off $part2base +$filesize; " \
855 "erase $part2base +$filesize; " \
856 "cp.b $loadaddr $part2base $filesize; " \
857 "echo Verifying...; " \
858 "cmp.b $loadaddr $part2base $filesize\0" \
859"ramboot=setenv bootargs root=/dev/ram ramdisk_size=$ramdisk_size ro" \
860 " console=$consoledev,$baudrate $othbootargs; " \
861 "tftp $rootfsaddr $rootfsfile; " \
862 "tftp $loadaddr $kernelfile; " \
863 "tftp $dtbaddr $dtbfile; " \
864 "bootm $loadaddr $rootfsaddr $dtbaddr\0" \
865"ramdisk_size=120000\0" \
866"ramdiskfile=rootfs.ext2.gz.uboot\0" \
867"releasefpga=mw.l 0xffe0f000 0x00400000; mw.l 0xffe0f004 0x00000000; " \
868 "mw.l 0xffe0f008 0x00400000\0" \
869"rootfsaddr=0x02F00000\0" \
870"rootfsfile=rootfs.ext2.gz.uboot\0" \
871"rootpath=/opt/nfsroot\0" \
872"spi__mbr=fatload mmc $mmcpart $loadaddr $mmbr; " \
873 "sf probe 0; sf erase 0 +$filesize; " \
874 "sf write $loadaddr 0 $filesize\0" \
875"spi__boot=fatload mmc $mmcpart $loadaddr u-boot.bin; " \
876 "protect off 0xeC000000 +$filesize; " \
877 "erase 0xEC000000 +$filesize; " \
878 "cp.b $loadaddr 0xEC000000 $filesize; " \
879 "cmp.b $loadaddr 0xEC000000 $filesize; " \
880 "protect on 0xeC000000 +$filesize\0" \
881"tftpflash=tftpboot $loadaddr $uboot; " \
882 "protect off " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
883 "erase " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
884 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize; " \
885 "protect on " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " +$filesize; " \
886 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE_NOR) " $filesize\0"\
887"uboot= " __stringify(CONFIG_UBOOTPATH) "\0" \
888"ubootfile=u-boot.bin\0" \
889"upgrade=run flashuboot\0" \
890"usb_phy_type=ulpi\0 " \
891"boot_nfs= " \
892 "setenv bootargs root=/dev/nfs rw " \
893 "nfsroot=$serverip:$rootpath " \
894 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
895 "console=$consoledev,$baudrate $othbootargs;" \
896 "tftp $loadaddr $bootfile;" \
897 "tftp $fdtaddr $fdtfile;" \
898 "bootm $loadaddr - $fdtaddr\0" \
899"boot_hd = " \
900 "setenv bootargs root=/dev/$bdev rw rootdelay=30 " \
901 "console=$consoledev,$baudrate $othbootargs;" \
902 "usb start;" \
903 "ext2load usb 0:1 $loadaddr /boot/$bootfile;" \
904 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;" \
905 "bootm $loadaddr - $fdtaddr\0" \
906"boot_usb_fat = " \
907 "setenv bootargs root=/dev/ram rw " \
908 "console=$consoledev,$baudrate $othbootargs " \
909 "ramdisk_size=$ramdisk_size;" \
910 "usb start;" \
911 "fatload usb 0:2 $loadaddr $bootfile;" \
912 "fatload usb 0:2 $fdtaddr $fdtfile;" \
913 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \
914 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
915"boot_usb_ext2 = " \
916 "setenv bootargs root=/dev/ram rw " \
917 "console=$consoledev,$baudrate $othbootargs " \
918 "ramdisk_size=$ramdisk_size;" \
919 "usb start;" \
920 "ext2load usb 0:4 $loadaddr $bootfile;" \
921 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
922 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
923 "bootm $loadaddr $ramdiskaddr $fdtaddr\0 " \
924"boot_nor = " \
925 "setenv bootargs root=/dev/$jffs2nor rw " \
926 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;" \
927 "bootm $norbootaddr - $norfdtaddr\0 " \
928"boot_ram = " \
929 "setenv bootargs root=/dev/ram rw " \
930 "console=$consoledev,$baudrate $othbootargs " \
931 "ramdisk_size=$ramdisk_size;" \
932 "tftp $ramdiskaddr $ramdiskfile;" \
933 "tftp $loadaddr $bootfile;" \
934 "tftp $fdtaddr $fdtfile;" \
935 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"
936
937#endif
938#endif
939
940#endif /* __CONFIG_H */