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Stefan Roeseae9996c2015-11-18 11:06:09 +01001/*
2 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6#ifndef __CONFIG_SOCFPGA_SR1500_H__
7#define __CONFIG_SOCFPGA_SR1500_H__
8
9#include <asm/arch/base_addr_ac5.h>
10
11#define CONFIG_BOARD_EARLY_INIT_F
12
13#define CONFIG_SYS_NO_FLASH
14#define CONFIG_DOS_PARTITION
15#define CONFIG_FAT_WRITE
16
17#define CONFIG_HW_WATCHDOG
18
19/* U-Boot Commands */
20#define CONFIG_CMD_ASKENV
21#define CONFIG_CMD_BOOTZ
22#define CONFIG_CMD_CACHE
23#define CONFIG_CMD_DHCP
24#define CONFIG_CMD_EXT4
25#define CONFIG_CMD_EXT4_WRITE
26#define CONFIG_CMD_FAT
27#define CONFIG_CMD_FS_GENERIC
28#define CONFIG_CMD_GPIO
29#define CONFIG_CMD_GREPENV
30#define CONFIG_CMD_MEMTEST
31#define CONFIG_CMD_MII
32#define CONFIG_CMD_MMC
33#define CONFIG_CMD_PING
34#define CONFIG_CMD_SF
35#define CONFIG_CMD_SPI
36#define CONFIG_CMD_TIME
37
38/* Memory configurations */
39#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SR1500 */
40
41/* Booting Linux */
42#define CONFIG_BOOTDELAY 3
43#define CONFIG_BOOTFILE "uImage"
44#define CONFIG_BOOTARGS "console=ttyS0" __stringify(CONFIG_BAUDRATE)
45#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
46#define CONFIG_LOADADDR 0x01000000
47#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
48#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
49
50/* Ethernet on SoC (EMAC) */
51#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
52/* The PHY is autodetected, so no MII PHY address is needed here */
53#define CONFIG_PHY_MARVELL
54#define PHY_ANEG_TIMEOUT 8000
55
Stefan Roeseae9996c2015-11-18 11:06:09 +010056#define CONFIG_EXTRA_ENV_SETTINGS \
57 "verify=n\0" \
58 "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
59 "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
60 "bootm ${loadaddr} - ${fdt_addr}\0" \
61 "bootimage=zImage\0" \
62 "fdt_addr=100\0" \
63 "fdtimage=socfpga.dtb\0" \
64 "fsloadcmd=ext2load\0" \
65 "bootm ${loadaddr} - ${fdt_addr}\0" \
66 "mmcroot=/dev/mmcblk0p2\0" \
67 "mmcboot=setenv bootargs " CONFIG_BOOTARGS \
68 " root=${mmcroot} rw rootwait;" \
69 "bootz ${loadaddr} - ${fdt_addr}\0" \
70 "mmcload=mmc rescan;" \
71 "load mmc 0:1 ${loadaddr} ${bootimage};" \
72 "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
Chin Liang Seeb3bb1112015-12-22 15:32:38 +080073 "qspiload=sf probe && mtdparts default && run ubiload\0" \
Stefan Roeseae9996c2015-11-18 11:06:09 +010074 "qspiboot=setenv bootargs " CONFIG_BOOTARGS \
Chin Liang See94f53a72015-12-22 15:32:42 +080075 " ubi.mtd=1,64 root=ubi0:rootfs rw rootfstype=ubifs;"\
76 "bootz ${loadaddr} - ${fdt_addr}\0" \
Chin Liang Seeeb450222015-12-22 15:32:34 +080077 "ubiload=ubi part UBI && ubifsmount ubi0 && " \
78 "ubifsload ${loadaddr} /boot/${bootimage} && " \
79 "ubifsload ${fdt_addr} /boot/${fdtimage}\0"
Stefan Roeseae9996c2015-11-18 11:06:09 +010080
81/* Environment */
82#define CONFIG_ENV_IS_IN_SPI_FLASH
83
84/* Enable SPI NOR flash reset, needed for SPI booting */
85#define CONFIG_SPI_N25Q256A_RESET
86
87/*
88 * Bootcounter
89 */
90#define CONFIG_BOOTCOUNT_LIMIT
91/* last 2 lwords in OCRAM */
92#define CONFIG_SYS_BOOTCOUNT_ADDR 0xfffffff8
93#define CONFIG_SYS_BOOTCOUNT_BE
94
95/* The rest of the configuration is shared */
96#include <configs/socfpga_common.h>
97
98/* U-Boot payload is stored at offset 0x60000 */
99#undef CONFIG_SYS_SPI_U_BOOT_OFFS
100#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x60000
101
102/* Environment setting for SPI flash */
103#undef CONFIG_ENV_SIZE
104#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
105#define CONFIG_ENV_SECT_SIZE (64 * 1024)
106#define CONFIG_ENV_SIZE (16 * 1024)
107#define CONFIG_ENV_OFFSET 0x00040000
108#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
109#define CONFIG_ENV_SPI_BUS 0
110#define CONFIG_ENV_SPI_CS 0
111#define CONFIG_ENV_SPI_MODE SPI_MODE_3
112#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
113
114#endif /* __CONFIG_SOCFPGA_SR1500_H__ */