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Timur Tabi2ad6b512006-10-31 18:44:42 -06001/*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006. All rights reserved.
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24
25#ifdef CONFIG_PCI
26
27#include <asm/mmu.h>
28#include <asm/global_data.h>
29#include <pci.h>
30#include <asm/mpc8349_pci.h>
31#include <i2c.h>
Kim Phillips94fab252007-12-20 16:28:34 -060032#if defined(CONFIG_OF_LIBFDT)
Kim Phillips3fde9e82007-08-15 22:30:33 -050033#include <libfdt.h>
Kim Phillips5b8bc602007-12-20 14:09:22 -060034#include <fdt_support.h>
Timur Tabibe5e6182006-11-03 19:15:00 -060035#endif
Timur Tabi2ad6b512006-10-31 18:44:42 -060036
37DECLARE_GLOBAL_DATA_PTR;
38
39/* System RAM mapped to PCI space */
40#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
41#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
42
43#ifndef CONFIG_PCI_PNP
44static struct pci_config_table pci_mpc8349itx_config_table[] = {
45 {
46 PCI_ANY_ID,
47 PCI_ANY_ID,
48 PCI_ANY_ID,
49 PCI_ANY_ID,
50 PCI_IDSEL_NUMBER,
51 PCI_ANY_ID,
52 pci_cfgfunc_config_device,
53 {
54 PCI_ENET0_IOADDR,
55 PCI_ENET0_MEMADDR,
56 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
57 },
58 {}
59};
60#endif
61
62static struct pci_controller pci_hose[] = {
63 {
64#ifndef CONFIG_PCI_PNP
65 config_table:pci_mpc8349itx_config_table,
66#endif
67 },
68 {
69#ifndef CONFIG_PCI_PNP
70 config_table:pci_mpc8349itx_config_table,
71#endif
72 }
73};
74
75/**************************************************************************
76 * pci_init_board()
77 *
78 * NOTICE: PCI2 is not currently supported
79 *
80 */
81void pci_init_board(void)
82{
83 volatile immap_t *immr;
84 volatile clk83xx_t *clk;
85 volatile law83xx_t *pci_law;
86 volatile pot83xx_t *pci_pot;
87 volatile pcictrl83xx_t *pci_ctrl;
88 volatile pciconf83xx_t *pci_conf;
89 u8 reg8;
90 u16 reg16;
91 u32 reg32;
92 u32 dev;
93 struct pci_controller *hose;
94
Timur Tabid239d742006-11-03 12:00:28 -060095 immr = (immap_t *) CFG_IMMR;
Timur Tabi2ad6b512006-10-31 18:44:42 -060096 clk = (clk83xx_t *) & immr->clk;
97 pci_law = immr->sysconf.pcilaw;
98 pci_pot = immr->ios.pot;
99 pci_ctrl = immr->pci_ctrl;
100 pci_conf = immr->pci_conf;
101
102 hose = &pci_hose[0];
103
104 /*
105 * Configure PCI controller and PCI_CLK_OUTPUT both in 66M mode
106 */
107
108 reg32 = clk->occr;
109 udelay(2000);
110
111#ifdef CONFIG_HARD_I2C
Timur Tabibe5e6182006-11-03 19:15:00 -0600112 i2c_set_bus_num(1);
Timur Tabi2ad6b512006-10-31 18:44:42 -0600113 /* Read the PCI_M66EN jumper setting */
114 if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
115 (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
116 if (reg8 & I2C_8574_PCI66)
117 clk->occr = 0xff000000; /* 66 MHz PCI */
118 else
119 clk->occr = 0xff600001; /* 33 MHz PCI */
120 } else {
121 clk->occr = 0xff600001; /* 33 MHz PCI */
122 }
123#else
124 clk->occr = 0xff000000; /* 66 MHz PCI */
125#endif
126
127 udelay(2000);
128
129 /*
130 * Release PCI RST Output signal
131 */
132 pci_ctrl[0].gcr = 0;
133 udelay(2000);
134 pci_ctrl[0].gcr = 1;
135
136#ifdef CONFIG_MPC83XX_PCI2
137 pci_ctrl[1].gcr = 0;
138 udelay(2000);
139 pci_ctrl[1].gcr = 1;
140#endif
141
142 /* We need to wait at least a 1sec based on PCI specs */
143 {
144 int i;
145
146 for (i = 0; i < 1000; i++)
147 udelay(1000);
148 }
149
150 /*
151 * Configure PCI Local Access Windows
152 */
153 pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
154 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
155
156 pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
Timur Tabi98883332006-10-31 19:14:41 -0600157 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600158
159 /*
160 * Configure PCI Outbound Translation Windows
161 */
162
163 /* PCI1 mem space - prefetch */
164 pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
165 pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
Timur Tabi98883332006-10-31 19:14:41 -0600166 pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600167
168 /* PCI1 IO space */
169 pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
170 pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
Timur Tabi98883332006-10-31 19:14:41 -0600171 pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600172
173 /* PCI1 mmio - non-prefetch mem space */
174 pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
175 pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
Timur Tabi98883332006-10-31 19:14:41 -0600176 pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600177
178 /*
179 * Configure PCI Inbound Translation Windows
180 */
181
182 /* we need RAM mapped to PCI space for the devices to
183 * access main memory */
184 pci_ctrl[0].pitar1 = 0x0;
185 pci_ctrl[0].pibar1 = 0x0;
186 pci_ctrl[0].piebar1 = 0x0;
187 pci_ctrl[0].piwar1 = PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP |
188 PIWAR_WTT_SNOOP | (__ilog2(gd->ram_size) - 1);
189
190 hose->first_busno = 0;
191 hose->last_busno = 0xff;
192
193 /* PCI memory prefetch space */
194 pci_set_region(hose->regions + 0,
195 CFG_PCI1_MEM_BASE,
196 CFG_PCI1_MEM_PHYS,
197 CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
198
199 /* PCI memory space */
200 pci_set_region(hose->regions + 1,
201 CFG_PCI1_MMIO_BASE,
202 CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);
203
204 /* PCI IO space */
205 pci_set_region(hose->regions + 2,
206 CFG_PCI1_IO_BASE,
207 CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
208
209 /* System memory space */
210 pci_set_region(hose->regions + 3,
211 CONFIG_PCI_SYS_MEM_BUS,
212 CONFIG_PCI_SYS_MEM_PHYS,
213 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
214
215 hose->region_count = 4;
216
217 pci_setup_indirect(hose,
Timur Tabid239d742006-11-03 12:00:28 -0600218 (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
Timur Tabi2ad6b512006-10-31 18:44:42 -0600219
220 pci_register_hose(hose);
221
222 /*
223 * Write to Command register
224 */
225 reg16 = 0xff;
226 dev = PCI_BDF(hose->first_busno, 0, 0);
227 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
228 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
229 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
230
231 /*
232 * Clear non-reserved bits in status register.
233 */
234 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
235 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
236 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
237
238#ifdef CONFIG_PCI_SCAN_SHOW
239 printf("PCI: Bus Dev VenId DevId Class Int\n");
240#endif
241 /*
242 * Hose scan.
243 */
244 hose->last_busno = pci_hose_scan(hose);
245
246#ifdef CONFIG_MPC83XX_PCI2
247 hose = &pci_hose[1];
248
249 /*
250 * Configure PCI Outbound Translation Windows
251 */
252
253 /* PCI2 mem space - prefetch */
254 pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
255 pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
Timur Tabi98883332006-10-31 19:14:41 -0600256 pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600257
258 /* PCI2 IO space */
259 pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
260 pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
Timur Tabi98883332006-10-31 19:14:41 -0600261 pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600262
263 /* PCI2 mmio - non-prefetch mem space */
264 pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
265 pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
Timur Tabi98883332006-10-31 19:14:41 -0600266 pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
Timur Tabi2ad6b512006-10-31 18:44:42 -0600267
268 /*
269 * Configure PCI Inbound Translation Windows
270 */
271
272 /* we need RAM mapped to PCI space for the devices to
273 * access main memory */
274 pci_ctrl[1].pitar1 = 0x0;
275 pci_ctrl[1].pibar1 = 0x0;
276 pci_ctrl[1].piebar1 = 0x0;
277 pci_ctrl[1].piwar1 =
278 PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
279 (__ilog2(gd->ram_size) - 1);
280
281 hose->first_busno = pci_hose[0].last_busno + 1;
282 hose->last_busno = 0xff;
283
284 /* PCI memory prefetch space */
285 pci_set_region(hose->regions + 0,
286 CFG_PCI2_MEM_BASE,
287 CFG_PCI2_MEM_PHYS,
288 CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
289
290 /* PCI memory space */
291 pci_set_region(hose->regions + 1,
292 CFG_PCI2_MMIO_BASE,
293 CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);
294
295 /* PCI IO space */
296 pci_set_region(hose->regions + 2,
297 CFG_PCI2_IO_BASE,
298 CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);
299
300 /* System memory space */
301 pci_set_region(hose->regions + 3,
302 CONFIG_PCI_SYS_MEM_BUS,
303 CONFIG_PCI_SYS_MEM_PHYS,
304 gd->ram_size, PCI_REGION_MEM | PCI_REGION_MEMORY);
305
306 hose->region_count = 4;
307
308 pci_setup_indirect(hose,
Timur Tabid239d742006-11-03 12:00:28 -0600309 (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));
Timur Tabi2ad6b512006-10-31 18:44:42 -0600310
311 pci_register_hose(hose);
312
313 /*
314 * Write to Command register
315 */
316 reg16 = 0xff;
317 dev = PCI_BDF(hose->first_busno, 0, 0);
318 pci_hose_read_config_word(hose, dev, PCI_COMMAND, &reg16);
319 reg16 |= PCI_COMMAND_SERR | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
320 pci_hose_write_config_word(hose, dev, PCI_COMMAND, reg16);
321
322 /*
323 * Clear non-reserved bits in status register.
324 */
325 pci_hose_write_config_word(hose, dev, PCI_STATUS, 0xffff);
326 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
327 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
328
329 /*
330 * Hose scan.
331 */
332 hose->last_busno = pci_hose_scan(hose);
333#endif
334}
335
Kim Phillips3fde9e82007-08-15 22:30:33 -0500336#if defined(CONFIG_OF_LIBFDT)
Kim Phillips5b8bc602007-12-20 14:09:22 -0600337void ft_pci_setup(void *blob, bd_t *bd)
Kim Phillips3fde9e82007-08-15 22:30:33 -0500338{
339 int nodeoffset;
Kim Phillips3fde9e82007-08-15 22:30:33 -0500340 int tmp[2];
Kim Phillips5b8bc602007-12-20 14:09:22 -0600341 const char *path;
Kim Phillips3fde9e82007-08-15 22:30:33 -0500342
Kim Phillips5b8bc602007-12-20 14:09:22 -0600343 nodeoffset = fdt_path_offset(blob, "/aliases");
Kim Phillips3fde9e82007-08-15 22:30:33 -0500344 if (nodeoffset >= 0) {
Kim Phillips5b8bc602007-12-20 14:09:22 -0600345 path = fdt_getprop(blob, nodeoffset, "pci0", NULL);
346 if (path) {
347 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
348 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
349 do_fixup_by_path(blob, path, "bus-range",
350 &tmp, sizeof(tmp), 1);
Kim Phillips3fde9e82007-08-15 22:30:33 -0500351
Kim Phillips5b8bc602007-12-20 14:09:22 -0600352 tmp[0] = cpu_to_be32(gd->pci_clk);
353 do_fixup_by_path(blob, path, "clock-frequency",
354 &tmp, sizeof(tmp[0]), 1);
355 }
Kim Phillips3fde9e82007-08-15 22:30:33 -0500356#ifdef CONFIG_MPC83XX_PCI2
Kim Phillips5b8bc602007-12-20 14:09:22 -0600357 path = fdt_getprop(blob, nodeoffset, "pci1", NULL);
358 if (path) {
359 tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
360 tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
361 do_fixup_by_path(blob, path, "bus-range",
362 &tmp, sizeof(tmp), 1);
Kim Phillips3fde9e82007-08-15 22:30:33 -0500363
Kim Phillips5b8bc602007-12-20 14:09:22 -0600364 tmp[0] = cpu_to_be32(gd->pci_clk);
365 do_fixup_by_path(blob, path, "clock-frequency",
366 &tmp, sizeof(tmp[0]), 1);
367 }
Kim Phillips3fde9e82007-08-15 22:30:33 -0500368#endif
Kim Phillips5b8bc602007-12-20 14:09:22 -0600369 }
Kim Phillips3fde9e82007-08-15 22:30:33 -0500370}
Kim Phillips94fab252007-12-20 16:28:34 -0600371#endif /* CONFIG_OF_LIBFDT */
Kim Phillips3fde9e82007-08-15 22:30:33 -0500372#endif /* CONFIG_PCI */