| Wolfgang Denk | 72a087e | 2006-10-24 14:27:35 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2005-2006 Atmel Corporation |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| Haavard Skinnemoen | 03d1e13 | 2006-11-18 18:01:13 +0100 | [diff] [blame] | 22 | #ifndef __AT32AP7000_MEMORY_MAP_H__ |
| 23 | #define __AT32AP7000_MEMORY_MAP_H__ |
| Wolfgang Denk | 72a087e | 2006-10-24 14:27:35 +0200 | [diff] [blame] | 24 | |
| Haavard Skinnemoen | 03d1e13 | 2006-11-18 18:01:13 +0100 | [diff] [blame] | 25 | /* Devices on the High Speed Bus (HSB) */ |
| 26 | #define LCDC_BASE 0xFF000000 |
| 27 | #define DMAC_BASE 0xFF200000 |
| 28 | #define USB_FIFO 0xFF300000 |
| Wolfgang Denk | 72a087e | 2006-10-24 14:27:35 +0200 | [diff] [blame] | 29 | |
| Haavard Skinnemoen | 03d1e13 | 2006-11-18 18:01:13 +0100 | [diff] [blame] | 30 | /* Devices on Peripheral Bus A (PBA) */ |
| 31 | #define SPI0_BASE 0xFFE00000 |
| 32 | #define SPI1_BASE 0xFFE00400 |
| 33 | #define TWI_BASE 0xFFE00800 |
| 34 | #define USART0_BASE 0xFFE00C00 |
| 35 | #define USART1_BASE 0xFFE01000 |
| 36 | #define USART2_BASE 0xFFE01400 |
| 37 | #define USART3_BASE 0xFFE01800 |
| 38 | #define SSC0_BASE 0xFFE01C00 |
| 39 | #define SSC1_BASE 0xFFE02000 |
| 40 | #define SSC2_BASE 0xFFE02400 |
| 41 | #define PIOA_BASE 0xFFE02800 |
| 42 | #define PIOB_BASE 0xFFE02C00 |
| 43 | #define PIOC_BASE 0xFFE03000 |
| 44 | #define PIOD_BASE 0xFFE03400 |
| 45 | #define PIOE_BASE 0xFFE03800 |
| 46 | #define PSIF_BASE 0xFFE03C00 |
| 47 | |
| 48 | /* Devices on Peripheral Bus B (PBB) */ |
| 49 | #define SM_BASE 0xFFF00000 |
| 50 | #define INTC_BASE 0xFFF00400 |
| 51 | #define HMATRIX_BASE 0xFFF00800 |
| 52 | #define TIMER0_BASE 0xFFF00C00 |
| 53 | #define TIMER1_BASE 0xFFF01000 |
| 54 | #define PWM_BASE 0xFFF01400 |
| 55 | #define MACB0_BASE 0xFFF01800 |
| 56 | #define MACB1_BASE 0xFFF01C00 |
| 57 | #define DAC_BASE 0xFFF02000 |
| 58 | #define MMCI_BASE 0xFFF02400 |
| 59 | #define AUDIOC_BASE 0xFFF02800 |
| 60 | #define HISI_BASE 0xFFF02C00 |
| 61 | #define USB_BASE 0xFFF03000 |
| 62 | #define HSMC_BASE 0xFFF03400 |
| 63 | #define HSDRAMC_BASE 0xFFF03800 |
| 64 | #define ECC_BASE 0xFFF03C00 |
| 65 | |
| 66 | #endif /* __AT32AP7000_MEMORY_MAP_H__ */ |