blob: 16d4e2e355cb1c00e03d31a7268a60143b98a6a1 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Andy Yan2c1e11d2017-06-01 18:00:55 +08002/*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
Andy Yan2c1e11d2017-06-01 18:00:55 +08004 */
5#ifndef __CONFIG_RV1108_COMMON_H
6#define __CONFIG_RV1108_COMMON_H
7
8#include <asm/arch/hardware.h>
9#include "rockchip-common.h"
10
Andy Yan2c1e11d2017-06-01 18:00:55 +080011#define CONFIG_SYS_MALLOC_LEN (32 << 20)
12#define CONFIG_SYS_CBSIZE 1024
13#define CONFIG_SKIP_LOWLEVEL_INIT
14
15#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
16/* TIMER1,initialized by ddr initialize code */
17#define CONFIG_SYS_TIMER_BASE 0x10350020
18#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
19
Otavio Salvador66d86af2018-11-30 11:34:13 -020020/* MMC/SD IP block */
21#define CONFIG_BOUNCE_BUFFER
22
Andy Yan2c1e11d2017-06-01 18:00:55 +080023#define CONFIG_SYS_SDRAM_BASE 0x60000000
Andy Yan2c1e11d2017-06-01 18:00:55 +080024#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
25#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
26
William Wucbeedaf2017-08-09 11:36:27 +080027/* rockchip ohci host driver */
28#define CONFIG_USB_OHCI_NEW
29#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
Andy Yan2c1e11d2017-06-01 18:00:55 +080030#endif
Otavio Salvadord3f4bce2018-11-30 11:34:17 -020031
32#ifndef CONFIG_SPL_BUILD
33#define ENV_MEM_LAYOUT_SETTINGS \
34 "scriptaddr=0x60000000\0" \
35 "fdt_addr_r=0x61f00000\0" \
36 "kernel_addr_r=0x62000000\0" \
37 "ramdisk_addr_r=0x64000000\0"
38
39#include <config_distro_bootcmd.h>
40#define CONFIG_EXTRA_ENV_SETTINGS \
41 ENV_MEM_LAYOUT_SETTINGS \
42 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
43 "partitions=" PARTS_DEFAULT \
44 BOOTENV
45#endif