blob: 74e6204db9e94eb51daed075bba639c40334243d [file] [log] [blame]
wdenk652a10c2005-01-09 23:48:14 +00001/*
2 * (C) Copyright 2001
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#include <common.h>
24#include <asm/processor.h>
25#include <command.h>
26#include <malloc.h>
27#include <spd_sdram.h>
28
29
30int board_early_init_f (void)
31{
32 /*
33 * IRQ 0-15 405GP internally generated; active high; level sensitive
34 * IRQ 16 405GP internally generated; active low; level sensitive
35 * IRQ 17-24 RESERVED
36 * IRQ 25 (EXT IRQ 0) CAN0; active low; level sensitive
37 * IRQ 26 (EXT IRQ 1) SER0 ; active low; level sensitive
38 * IRQ 27 (EXT IRQ 2) SER1; active low; level sensitive
39 * IRQ 28 (EXT IRQ 3) FPGA 0; active low; level sensitive
40 * IRQ 29 (EXT IRQ 4) FPGA 1; active low; level sensitive
41 * IRQ 30 (EXT IRQ 5) PCI INTA; active low; level sensitive
42 * IRQ 31 (EXT IRQ 6) COMPACT FLASH; active high; level sensitive
43 */
Stefan Roese952e7762009-09-24 09:55:50 +020044 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
45 mtdcr(UIC0ER, 0x00000000); /* disable all ints */
46 mtdcr(UIC0CR, 0x00000000); /* set all to be non-critical*/
47 mtdcr(UIC0PR, 0xFFFFFF81); /* set int polarities */
48 mtdcr(UIC0TR, 0x10000000); /* set int trigger levels */
49 mtdcr(UIC0VCR, 0x00000001); /* set vect base=0,INT0 highest priority*/
50 mtdcr(UIC0SR, 0xFFFFFFFF); /* clear all ints */
wdenk652a10c2005-01-09 23:48:14 +000051
52 /*
53 * EBC Configuration Register: set ready timeout to 512 ebc-clks -> ca. 15 us
54 */
Stefan Roesed1c3b272009-09-09 16:25:29 +020055 mtebc (EBC0_CFG, 0xa8400000);
wdenk652a10c2005-01-09 23:48:14 +000056
57 return 0;
58}
59
60
61/* ------------------------------------------------------------------------- */
62
63int misc_init_f (void)
64{
65 return 0; /* dummy implementation */
66}
67
68
69int misc_init_r (void)
70{
71 return (0);
72}
73
74
75/*
76 * Check Board Identity:
77 */
78
79int checkboard (void)
80{
Wolfgang Denk77ddac92005-10-13 16:45:02 +020081 char str[64];
wdenk652a10c2005-01-09 23:48:14 +000082 int i = getenv_r ("serial#", str, sizeof(str));
83
84 puts ("Board: ");
85
86 if (i == -1) {
87 puts ("### No HW ID - assuming sbc405");
88 } else {
89 puts(str);
90 }
91
92 putc ('\n');
93
94 return 0;
95}
96
97/* ------------------------------------------------------------------------- */
98
Becky Bruce9973e3c2008-06-09 16:03:40 -050099phys_size_t initdram (int board_type)
wdenk652a10c2005-01-09 23:48:14 +0000100{
Wolfgang Denkd87080b2006-03-31 18:32:53 +0200101 return spd_sdram ();
wdenk652a10c2005-01-09 23:48:14 +0000102}
103
104/* ------------------------------------------------------------------------- */
105
106int testdram (void)
107{
108 /* TODO: XXX XXX XXX */
109 printf ("test: 64 MB - ok\n");
110
111 return (0);
112}
113
114/* ------------------------------------------------------------------------- */