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Siva Durga Prasad Paladugud1f4e392018-04-19 12:37:09 +05301/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Xilinx ZynqMP SoC Tap Delay Programming
4 *
5 * Copyright (C) 2018 Xilinx, Inc.
6 */
7
8#ifndef __ZYNQMP_TAP_DELAY_H__
9#define __ZYNQMP_TAP_DELAY_H__
10
11#ifdef CONFIG_ARCH_ZYNQMP
12void zynqmp_dll_reset(u8 deviceid);
Ashok Reddy Soma728d21b2020-10-23 04:59:04 -060013void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay, u32 otap_delay);
Siva Durga Prasad Paladugud1f4e392018-04-19 12:37:09 +053014#else
15inline void zynqmp_dll_reset(u8 deviceid) {}
Ashok Reddy Soma728d21b2020-10-23 04:59:04 -060016inline void arasan_zynqmp_set_tapdelay(u8 device_id, u32 itap_delay,
17 u32 otap_delay) {}
Siva Durga Prasad Paladugud1f4e392018-04-19 12:37:09 +053018#endif
19
20#endif