Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Bluewater Systems Snapper 9260 and 9G20 modules |
| 3 | * |
| 4 | * (C) Copyright 2011 Bluewater Systems |
| 5 | * Author: Andre Renaud <andre@bluewatersys.com> |
| 6 | * Author: Ryan Mallon <ryan@bluewatersys.com> |
| 7 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 8 | * SPDX-License-Identifier: GPL-2.0+ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 9 | */ |
| 10 | |
| 11 | #ifndef __CONFIG_H |
| 12 | #define __CONFIG_H |
| 13 | |
| 14 | /* SoC type is defined in boards.cfg */ |
| 15 | #include <asm/hardware.h> |
Alexey Brodkin | 1ace402 | 2014-02-26 17:47:58 +0400 | [diff] [blame] | 16 | #include <linux/sizes.h> |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 17 | |
Simon Glass | 5e8a749 | 2014-10-29 13:08:55 -0600 | [diff] [blame] | 18 | #define CONFIG_SYS_TEXT_BASE 0x21f00000 |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 19 | |
| 20 | /* ARM asynchronous clock */ |
| 21 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */ |
| 22 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 23 | |
| 24 | /* CPU */ |
| 25 | #define CONFIG_ARCH_CPU_INIT |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 26 | |
| 27 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
| 28 | #define CONFIG_SETUP_MEMORY_TAGS |
| 29 | #define CONFIG_INITRD_TAG |
| 30 | #define CONFIG_SKIP_LOWLEVEL_INIT |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 31 | #define CONFIG_DISPLAY_CPUINFO |
| 32 | #define CONFIG_FIT |
| 33 | |
| 34 | /* SDRAM */ |
| 35 | #define CONFIG_NR_DRAM_BANKS 1 |
| 36 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 |
| 37 | #define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */ |
| 38 | #define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \ |
| 39 | GENERATED_GBL_DATA_SIZE) |
| 40 | |
| 41 | /* Mem test settings */ |
| 42 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE |
| 43 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024)) |
| 44 | |
| 45 | /* NAND Flash */ |
| 46 | #define CONFIG_NAND_ATMEL |
| 47 | #define CONFIG_SYS_NO_FLASH |
| 48 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
| 49 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 |
| 50 | #define CONFIG_SYS_NAND_DBW_8 |
| 51 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ |
| 52 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */ |
| 53 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 |
| 54 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 |
| 55 | |
| 56 | /* Ethernet */ |
| 57 | #define CONFIG_MACB |
| 58 | #define CONFIG_RMII |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 59 | #define CONFIG_NET_RETRY_COUNT 20 |
| 60 | #define CONFIG_RESET_PHY_R |
Heiko Schocher | 4535a24 | 2013-11-18 08:07:23 +0100 | [diff] [blame] | 61 | #define CONFIG_AT91_WANTS_COMMON_PHY |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 62 | #define CONFIG_TFTP_PORT |
| 63 | #define CONFIG_TFTP_TSIZE |
| 64 | |
| 65 | /* USB */ |
| 66 | #define CONFIG_USB_ATMEL |
Bo Shen | dcd2f1a | 2013-10-21 16:14:00 +0800 | [diff] [blame] | 67 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 68 | #define CONFIG_USB_OHCI_NEW |
| 69 | #define CONFIG_DOS_PARTITION |
| 70 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
| 71 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE |
| 72 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" |
| 73 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 |
| 74 | #define CONFIG_USB_STORAGE |
| 75 | |
| 76 | /* GPIOs and IO expander */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 77 | #define CONFIG_ATMEL_LEGACY |
| 78 | #define CONFIG_AT91_GPIO |
| 79 | #define CONFIG_AT91_GPIO_PULLUP 1 |
| 80 | #define CONFIG_PCA953X |
| 81 | #define CONFIG_SYS_I2C_PCA953X_ADDR 0x28 |
| 82 | #define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} } |
| 83 | |
| 84 | /* UARTs/Serial console */ |
| 85 | #define CONFIG_ATMEL_USART |
Simon Glass | 1a1927f | 2014-10-29 13:09:01 -0600 | [diff] [blame] | 86 | #ifndef CONFIG_DM_SERIAL |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 87 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU |
| 88 | #define CONFIG_USART_ID ATMEL_ID_SYS |
Simon Glass | 1a1927f | 2014-10-29 13:09:01 -0600 | [diff] [blame] | 89 | #endif |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 90 | #define CONFIG_BAUDRATE 115200 |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 91 | |
| 92 | /* I2C - Bit-bashed */ |
Heiko Schocher | ea818db | 2013-01-29 08:53:15 +0100 | [diff] [blame] | 93 | #define CONFIG_SYS_I2C |
| 94 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
| 95 | #define CONFIG_SYS_I2C_SOFT_SPEED 100000 |
| 96 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 97 | #define CONFIG_SOFT_I2C_READ_REPEATED_START |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 98 | #define I2C_INIT do { \ |
| 99 | at91_set_gpio_output(AT91_PIN_PA23, 1); \ |
| 100 | at91_set_gpio_output(AT91_PIN_PA24, 1); \ |
| 101 | at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \ |
| 102 | at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \ |
| 103 | } while (0) |
| 104 | #define I2C_SOFT_DECLARATIONS |
| 105 | #define I2C_ACTIVE |
| 106 | #define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1); |
| 107 | #define I2C_READ at91_get_gpio_value(AT91_PIN_PA23); |
| 108 | #define I2C_SDA(bit) do { \ |
| 109 | if (bit) { \ |
| 110 | at91_set_gpio_input(AT91_PIN_PA23, 1); \ |
| 111 | } else { \ |
| 112 | at91_set_gpio_output(AT91_PIN_PA23, 1); \ |
| 113 | at91_set_gpio_value(AT91_PIN_PA23, bit); \ |
| 114 | } \ |
| 115 | } while (0) |
| 116 | #define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit) |
| 117 | #define I2C_DELAY udelay(2) |
| 118 | |
| 119 | /* Boot options */ |
| 120 | #define CONFIG_SYS_LOAD_ADDR 0x23000000 |
| 121 | #define CONFIG_BOOTDELAY 3 |
| 122 | #define CONFIG_ZERO_BOOTDELAY_CHECK |
| 123 | |
| 124 | #define CONFIG_BOOTP_BOOTFILESIZE |
| 125 | #define CONFIG_BOOTP_BOOTPATH |
| 126 | #define CONFIG_BOOTP_GATEWAY |
| 127 | #define CONFIG_BOOTP_HOSTNAME |
| 128 | |
| 129 | /* Environment settings */ |
| 130 | #define CONFIG_ENV_IS_IN_NAND |
| 131 | #define CONFIG_ENV_OFFSET (512 << 10) |
| 132 | #define CONFIG_ENV_SIZE (256 << 10) |
| 133 | #define CONFIG_ENV_OVERWRITE |
| 134 | #define CONFIG_BOOTARGS "console=ttyS0,115200 ip=any" |
| 135 | |
| 136 | /* Console settings */ |
| 137 | #define CONFIG_SYS_CBSIZE 256 |
| 138 | #define CONFIG_SYS_MAXARGS 16 |
| 139 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ |
| 140 | sizeof(CONFIG_SYS_PROMPT) + 16) |
| 141 | #define CONFIG_SYS_LONGHELP |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 142 | #define CONFIG_CMDLINE_EDITING |
| 143 | #define CONFIG_AUTO_COMPLETE |
| 144 | #define CONFIG_SYS_HUSH_PARSER |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 145 | |
| 146 | /* U-Boot memory settings */ |
| 147 | #define CONFIG_SYS_MALLOC_LEN (1 << 20) |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 148 | |
| 149 | /* Command line configuration */ |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 150 | #define CONFIG_CMD_PING |
| 151 | #define CONFIG_CMD_DHCP |
| 152 | #define CONFIG_CMD_FAT |
| 153 | #define CONFIG_CMD_I2C |
Simon Glass | 1a1927f | 2014-10-29 13:09:01 -0600 | [diff] [blame] | 154 | #define CONFIG_CMD_GPIO |
Ryan Mallon | b8d41dd | 2011-06-05 07:21:22 +0000 | [diff] [blame] | 155 | #define CONFIG_CMD_USB |
| 156 | #define CONFIG_CMD_MII |
| 157 | #define CONFIG_CMD_NAND |
| 158 | #define CONFIG_CMD_PCA953X |
| 159 | #define CONFIG_CMD_PCA953X_INFO |
| 160 | |
| 161 | #endif /* __CONFIG_H */ |