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TsiChungLiew4a442d32007-08-16 19:23:50 -05001/*
2 * Configuation settings for the Freescale MCF5329 FireEngine board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02007 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew4a442d32007-08-16 19:23:50 -05008 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5235EVB_H
15#define _M5235EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
TsiChungLiew4a442d32007-08-16 19:23:50 -050021
TsiChungLiew4a442d32007-08-16 19:23:50 -050022#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020023#define CONFIG_SYS_UART_PORT (0)
TsiChungLiew4a442d32007-08-16 19:23:50 -050024
25#undef CONFIG_WATCHDOG
26#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
27
28/*
29 * BOOTP options
30 */
31#define CONFIG_BOOTP_BOOTFILESIZE
TsiChungLiew4a442d32007-08-16 19:23:50 -050032
TsiChungLiew4a442d32007-08-16 19:23:50 -050033#define CONFIG_MCFFEC
34#ifdef CONFIG_MCFFEC
TsiChungLiew4a442d32007-08-16 19:23:50 -050035# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050036# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020037# define CONFIG_SYS_DISCOVER_PHY
38# define CONFIG_SYS_RX_ETH_BUFFER 8
39# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew4a442d32007-08-16 19:23:50 -050040
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020041# define CONFIG_SYS_FEC0_PINMUX 0
42# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020043# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
45# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew4a442d32007-08-16 19:23:50 -050046# define FECDUPLEX FULL
47# define FECSPEED _100BASET
48# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
50# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew4a442d32007-08-16 19:23:50 -050051# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew4a442d32007-08-16 19:23:50 -050053#endif
54
55/* Timer */
56#define CONFIG_MCFTMR
57#undef CONFIG_MCFPIT
58
59/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +020060#define CONFIG_SYS_I2C
61#define CONFIG_SYS_i2C_FSL
62#define CONFIG_SYS_FSL_I2C_SPEED 80000
63#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
64#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020065#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
66#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
67#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
68#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
TsiChungLiew4a442d32007-08-16 19:23:50 -050069
70/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
TsiChungLiew4a442d32007-08-16 19:23:50 -050071#define CONFIG_BOOTFILE "u-boot.bin"
72#ifdef CONFIG_MCFFEC
TsiChungLiew4a442d32007-08-16 19:23:50 -050073# define CONFIG_IPADDR 192.162.1.2
74# define CONFIG_NETMASK 255.255.255.0
75# define CONFIG_SERVERIP 192.162.1.1
76# define CONFIG_GATEWAYIP 192.162.1.1
TsiChungLiew4a442d32007-08-16 19:23:50 -050077#endif /* FEC_ENET */
78
Mario Six5bc05432018-03-28 14:38:20 +020079#define CONFIG_HOSTNAME "M5235EVB"
TsiChungLiew4a442d32007-08-16 19:23:50 -050080#define CONFIG_EXTRA_ENV_SETTINGS \
81 "netdev=eth0\0" \
82 "loadaddr=10000\0" \
83 "u-boot=u-boot.bin\0" \
84 "load=tftp ${loadaddr) ${u-boot}\0" \
85 "upd=run load; run prog\0" \
86 "prog=prot off ffe00000 ffe3ffff;" \
87 "era ffe00000 ffe3ffff;" \
88 "cp.b ${loadaddr} ffe00000 ${filesize};"\
89 "save\0" \
90 ""
91
92#define CONFIG_PRAM 512 /* 512 KB */
TsiChungLiew4a442d32007-08-16 19:23:50 -050093
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020094#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
TsiChungLiew4a442d32007-08-16 19:23:50 -050095
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020096#define CONFIG_SYS_CLK 75000000
97#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
TsiChungLiew4a442d32007-08-16 19:23:50 -050098
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020099#define CONFIG_SYS_MBAR 0x40000000
TsiChungLiew4a442d32007-08-16 19:23:50 -0500100
101/*
102 * Low Level Configuration Settings
103 * (address mappings, register initial values, etc.)
104 * You should know what you are doing if you make changes here.
105 */
106/*-----------------------------------------------------------------------
107 * Definitions for initial stack pointer and data area (in DPRAM)
108 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200110#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_INIT_RAM_CTRL 0x21
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200112#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
TsiChungLiew4a442d32007-08-16 19:23:50 -0500114
115/*-----------------------------------------------------------------------
116 * Start addresses for the final memory configuration
117 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiew4a442d32007-08-16 19:23:50 -0500119 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_SDRAM_BASE 0x00000000
121#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChungLiew4a442d32007-08-16 19:23:50 -0500122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
124#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiew4a442d32007-08-16 19:23:50 -0500125
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
127#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
TsiChungLiew4a442d32007-08-16 19:23:50 -0500128
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
130#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChungLiew4a442d32007-08-16 19:23:50 -0500131
132/*
133 * For booting Linux, the board info and command line data
134 * have to be in the first 8 MB of memory, since this is
135 * the maximum mapped by the Linux kernel during initialization ??
136 */
137/* Initial Memory map for Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChung Liewd6e4baf2009-01-27 12:57:47 +0000139#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
TsiChungLiew4a442d32007-08-16 19:23:50 -0500140
141/*-----------------------------------------------------------------------
142 * FLASH organization
143 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_FLASH_CFI
145#ifdef CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200146# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
TsiChungLiew4a442d32007-08-16 19:23:50 -0500148#ifdef NORFLASH_PS32BIT
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
TsiChungLiew4a442d32007-08-16 19:23:50 -0500150#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
TsiChungLiew4a442d32007-08-16 19:23:50 -0500152#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
154# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
155# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
TsiChungLiew4a442d32007-08-16 19:23:50 -0500156#endif
157
TsiChung Liew012522f2008-10-21 10:03:07 +0000158#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
TsiChungLiew4a442d32007-08-16 19:23:50 -0500159
160/* Configuration for environment
161 * Environment is embedded in u-boot in the second sector of the flash
162 */
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200163
164#define LDS_BOARD_TEXT \
165 . = DEFINED(env_offset) ? env_offset : .; \
Simon Glass0649cd02017-08-03 12:21:49 -0600166 env/embedded.o(.text);
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200167
TsiChungLiew4a442d32007-08-16 19:23:50 -0500168#ifdef NORFLASH_PS32BIT
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200169# define CONFIG_ENV_OFFSET (0x8000)
170# define CONFIG_ENV_SIZE 0x4000
171# define CONFIG_ENV_SECT_SIZE 0x4000
TsiChungLiew4a442d32007-08-16 19:23:50 -0500172#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200173# define CONFIG_ENV_OFFSET (0x4000)
174# define CONFIG_ENV_SIZE 0x2000
175# define CONFIG_ENV_SECT_SIZE 0x2000
TsiChungLiew4a442d32007-08-16 19:23:50 -0500176#endif
177
178/*-----------------------------------------------------------------------
179 * Cache Configuration
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiew4a442d32007-08-16 19:23:50 -0500182
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600183#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200184 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600185#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200186 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600187#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
188#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
189 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
190 CF_ACR_EN | CF_ACR_SM_ALL)
191#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
192 CF_CACR_CEIB | CF_CACR_DCM | \
193 CF_CACR_EUSP)
194
TsiChungLiew4a442d32007-08-16 19:23:50 -0500195/*-----------------------------------------------------------------------
196 * Chipselect bank definitions
197 */
198/*
199 * CS0 - NOR Flash 1, 2, 4, or 8MB
200 * CS1 - Available
201 * CS2 - Available
202 * CS3 - Available
203 * CS4 - Available
204 * CS5 - Available
205 * CS6 - Available
206 * CS7 - Available
207 */
208#ifdef NORFLASH_PS32BIT
TsiChung Liew012522f2008-10-21 10:03:07 +0000209# define CONFIG_SYS_CS0_BASE 0xFFC00000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210# define CONFIG_SYS_CS0_MASK 0x003f0001
TsiChung Liew012522f2008-10-21 10:03:07 +0000211# define CONFIG_SYS_CS0_CTRL 0x00001D00
TsiChungLiew4a442d32007-08-16 19:23:50 -0500212#else
TsiChung Liew012522f2008-10-21 10:03:07 +0000213# define CONFIG_SYS_CS0_BASE 0xFFE00000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214# define CONFIG_SYS_CS0_MASK 0x001f0001
TsiChung Liew012522f2008-10-21 10:03:07 +0000215# define CONFIG_SYS_CS0_CTRL 0x00001D80
TsiChungLiew4a442d32007-08-16 19:23:50 -0500216#endif
217
218#endif /* _M5329EVB_H */