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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
37#define CONFIG_ETX094 1 /* ...on a ETX_094 board */
38
Wolfgang Denk2ae18242010-10-06 09:05:45 +020039#define CONFIG_SYS_TEXT_BASE 0x40000000
40
wdenke2211742002-11-02 23:30:20 +000041#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
42#undef CONFIG_8xx_CONS_SMC2
43#undef CONFIG_8xx_CONS_NONE
44#define CONFIG_BAUDRATE 57600
45#if 0
46#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
47#else
48#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
49#endif
50
51#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
52
53#define CONFIG_BOARD_TYPES 1 /* support board types */
54
55#define CONFIG_FLASH_16BIT /* for board with 16bit wide flash */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020056#undef SB_ETX094 /* only for SB-Board with 16MB SDRAM */
wdenke2211742002-11-02 23:30:20 +000057#define CONFIG_BOOTP_RANDOM_DELAY /* graceful BOOTP recovery mode */
58
59#define CONFIG_ETHADDR 08:00:06:00:00:00
60
61#ifdef CONFIG_ETHADDR
62#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 /* default MAC can be overwritten once */
63#endif
64
65#undef CONFIG_BOOTARGS
66#define CONFIG_RAMBOOTCOMMAND \
67 "bootp; " \
68 "setenv bootargs root=/dev/ram rw ramdisk_size=4690 " \
69 "U-Boot_version=U-Boot-1.0.x-Date " \
70 "panic=1 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010071 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenke2211742002-11-02 23:30:20 +000072 "bootm"
73#define CONFIG_NFSBOOTCOMMAND \
74 "bootp; " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010075 "setenv bootargs root=/dev/nfs rw nfsroot=${nfsip}:${rootpath} " \
76 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenke2211742002-11-02 23:30:20 +000077 "bootm"
78#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
79
80#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenke2211742002-11-02 23:30:20 +000082
83#define CONFIG_WATCHDOG 1 /* watchdog enabled */
84
85#define CONFIG_STATUS_LED 1 /* Status LED enabled */
86
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050087
88/*
89 * BOOTP options
90 */
91#define CONFIG_BOOTP_SUBNETMASK
92#define CONFIG_BOOTP_GATEWAY
93#define CONFIG_BOOTP_HOSTNAME
94#define CONFIG_BOOTP_BOOTPATH
95#define CONFIG_BOOTP_BOOTFILESIZE
wdenke2211742002-11-02 23:30:20 +000096
Jon Loeligerdcaa7152007-07-07 20:56:05 -050097
98/*
99 * Command line configuration.
100 */
101#include <config_cmd_default.h>
102
wdenke2211742002-11-02 23:30:20 +0000103
104/*
105 * Miscellaneous configurable options
106 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_LONGHELP /* undef to save memory */
108#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500109#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000111#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000113#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200114#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
115#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
116#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
119#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000120
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000122
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke2211742002-11-02 23:30:20 +0000126
127/*
128 * Low Level Configuration Settings
129 * (address mappings, register initial values, etc.)
130 * You should know what you are doing if you make changes here.
131 */
132/*-----------------------------------------------------------------------
133 * Internal Memory Mapped Register
134 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_IMMR 0xFFF00000
wdenke2211742002-11-02 23:30:20 +0000136
137/*-----------------------------------------------------------------------
138 * Definitions for initial stack pointer and data area (in DPRAM)
139 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200141#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200142#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000144
145/*-----------------------------------------------------------------------
146 * Start addresses for the final memory configuration
147 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000149 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_SDRAM_BASE 0x00000000
151#define CONFIG_SYS_FLASH_BASE 0x40000000
wdenke2211742002-11-02 23:30:20 +0000152#ifdef DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenke2211742002-11-02 23:30:20 +0000154#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenke2211742002-11-02 23:30:20 +0000156#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
158#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000159
160/*
161 * For booting Linux, the board info and command line data
162 * have to be in the first 8 MB of memory, since this is
163 * the maximum mapped by the Linux kernel during initialization.
164 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000166/*-----------------------------------------------------------------------
167 * FLASH organization
168 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
170#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
173#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000174
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200175#define CONFIG_ENV_IS_IN_FLASH 1
wdenke2211742002-11-02 23:30:20 +0000176#ifdef CONFIG_FLASH_16BIT
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200177#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
178#define CONFIG_ENV_SIZE 0x8000 /* Total Size of Environment Sector */
wdenke2211742002-11-02 23:30:20 +0000179#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200180#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
181#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenke2211742002-11-02 23:30:20 +0000182#endif
183
184/*-----------------------------------------------------------------------
185 * Hardware Information Block
186 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
188#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
189#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenke2211742002-11-02 23:30:20 +0000190
191/*-----------------------------------------------------------------------
192 * Cache Configuration
193 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200194#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeligerdcaa7152007-07-07 20:56:05 -0500195#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000197#endif
198
199/*-----------------------------------------------------------------------
200 * SYPCR - System Protection Control 11-9
201 * SYPCR can only be written once after reset!
202 *-----------------------------------------------------------------------
203 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
204 */
205#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenke2211742002-11-02 23:30:20 +0000207 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
208#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenke2211742002-11-02 23:30:20 +0000210#endif /* CONFIG_WATCHDOG */
211
212/*-----------------------------------------------------------------------
213 * SIUMCR - SIU Module Configuration 11-6
214 *-----------------------------------------------------------------------
215 * PCMCIA config., multi-function pin tri-state
216 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenke2211742002-11-02 23:30:20 +0000218
219/*-----------------------------------------------------------------------
220 * TBSCR - Time Base Status and Control 11-26
221 *-----------------------------------------------------------------------
222 * Clear Reference Interrupt Status, Timebase freezing enabled
223 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenke2211742002-11-02 23:30:20 +0000225
226/*-----------------------------------------------------------------------
227 * RTCSC - Real-Time Clock Status and Control Register 11-27
228 *-----------------------------------------------------------------------
229 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenke2211742002-11-02 23:30:20 +0000231
232/*-----------------------------------------------------------------------
233 * PISCR - Periodic Interrupt Status and Control 11-31
234 *-----------------------------------------------------------------------
235 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
236 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenke2211742002-11-02 23:30:20 +0000238
239/*-----------------------------------------------------------------------
240 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
241 *-----------------------------------------------------------------------
242 * Reset PLL lock status sticky bit, timer expired status bit and timer
243 * interrupt status bit - leave PLL multiplication factor unchanged !
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenke2211742002-11-02 23:30:20 +0000246
247/*-----------------------------------------------------------------------
248 * SCCR - System Clock and reset Control Register 15-27
249 *-----------------------------------------------------------------------
250 * Set clock output, timebase and RTC source and divider,
251 * power management and some other internal clocks
252 */
253#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenke2211742002-11-02 23:30:20 +0000255 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
256 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
257 SCCR_DFALCD00)
258
259/*-----------------------------------------------------------------------
260 * PCMCIA stuff
261 *-----------------------------------------------------------------------
262 *
263 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
265#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
266#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
267#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
268#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
269#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
270#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
271#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenke2211742002-11-02 23:30:20 +0000272
273/*-----------------------------------------------------------------------
274 *
275 *-----------------------------------------------------------------------
276 *
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_DER 0
wdenke2211742002-11-02 23:30:20 +0000279
280/*
281 * Init Memory Controller:
282 *
283 * BR0/1 and OR0/1 (FLASH)
284 */
285
286#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
287#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
288
289/* used to re-map FLASH both when starting from SRAM or FLASH:
290 * restrict access enough to keep SRAM working (if any)
291 * but not too much to meddle with FLASH accesses
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
294#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenke2211742002-11-02 23:30:20 +0000295
296/* FLASH timing: ACS = 11, TRLX = 1, CSNT = 0, SCY = 2, EHTR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_BI | \
wdenk8bde7f72003-06-27 21:31:46 +0000298 OR_SCY_2_CLK | OR_TRLX )
wdenke2211742002-11-02 23:30:20 +0000299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
301#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
wdenke2211742002-11-02 23:30:20 +0000302
303#ifdef CONFIG_FLASH_16BIT /* 16 bit data port */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
305#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
wdenke2211742002-11-02 23:30:20 +0000306#else /* 32 bit data port */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
308#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V | BR_PS_32)
wdenke2211742002-11-02 23:30:20 +0000309#endif /* CONFIG_FLASH_16BIT */
310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
312#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
wdenke2211742002-11-02 23:30:20 +0000313
314/*
315 * BR2/3 and OR2/3 (SDRAM)
316 *
317 */
318#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
319#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
320#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
321
322/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200323#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenke2211742002-11-02 23:30:20 +0000324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
326#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke2211742002-11-02 23:30:20 +0000327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
329#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke2211742002-11-02 23:30:20 +0000330
331/*
332 * Memory Periodic Timer Prescaler
333 */
334
335/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_MAMR_PTA 23 /* start with divider for 100 MHz */
wdenke2211742002-11-02 23:30:20 +0000337
338/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
340#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenke2211742002-11-02 23:30:20 +0000341
342/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200343#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
344#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenke2211742002-11-02 23:30:20 +0000345
346/*
347 * MAMR settings for SDRAM
348 */
349
350/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke2211742002-11-02 23:30:20 +0000352 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
353 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X)
354/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200355#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenke2211742002-11-02 23:30:20 +0000356 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
357 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_1X)
358
wdenke2211742002-11-02 23:30:20 +0000359#endif /* __CONFIG_H */