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wdenka562e1b2005-01-09 18:21:42 +00001/*
2 * Configuation settings for the Sentec Cobra Board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenka562e1b2005-01-09 18:21:42 +00007 */
8
9/* ---
Bin Menga1875592016-02-05 19:30:11 -080010 * Version: U-Boot 1.0.0 - initial release for Sentec COBRA5272 board
wdenka562e1b2005-01-09 18:21:42 +000011 * Date: 2004-03-29
12 * Author: Florian Schlote
13 *
14 * For a description of configuration options please refer also to the
15 * general u-boot-1.x.x/README file
16 * ---
17 */
18
19/* ---
20 * board/config.h - configuration options, board specific
21 * ---
22 */
23
24#ifndef _CONFIG_COBRA5272_H
25#define _CONFIG_COBRA5272_H
26
27/* ---
wdenka562e1b2005-01-09 18:21:42 +000028 * Defines processor clock - important for correct timings concerning serial
29 * interface etc.
wdenka562e1b2005-01-09 18:21:42 +000030 * ---
31 */
32
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020033#define CONFIG_SYS_CLK 66000000
34#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
wdenka562e1b2005-01-09 18:21:42 +000035
36/* ---
37 * Enable use of Ethernet
38 * ---
39 */
TsiChungLiew67064242007-08-15 19:41:06 -050040#define CONFIG_MCFFEC
wdenka562e1b2005-01-09 18:21:42 +000041
TsiChungLiew67064242007-08-15 19:41:06 -050042/* Enable Dma Timer */
43#define CONFIG_MCFTMR
wdenka562e1b2005-01-09 18:21:42 +000044
45/* ---
46 * Define baudrate for UART1 (console output, tftp, ...)
47 * default value of CONFIG_BAUDRATE for Sentec board: 19200 baud
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048 * CONFIG_SYS_BAUDRATE_TABLE defines values that can be selected in u-boot command
wdenka562e1b2005-01-09 18:21:42 +000049 * interface
50 * ---
51 */
52
TsiChungLiew67064242007-08-15 19:41:06 -050053#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020054#define CONFIG_SYS_UART_PORT (0)
wdenka562e1b2005-01-09 18:21:42 +000055
56/* ---
57 * set "#if 0" to "#if 1" if (Hardware)-WATCHDOG should be enabled & change
58 * timeout acc. to your needs
59 * #define CONFIG_WATCHDOG_TIMEOUT x , x is timeout in milliseconds, e. g. 10000
60 * for 10 sec
61 * ---
62 */
63
64#if 0
65#define CONFIG_WATCHDOG
66#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
67#endif
68
69/* ---
70 * CONFIG_MONITOR_IS_IN_RAM defines if u-boot is started from a different
71 * bootloader residing in flash ('chainloading'); if you want to use
72 * chainloading or want to compile a u-boot binary that can be loaded into
73 * RAM via BDM set
Wolfgang Denk53677ef2008-05-20 16:00:29 +020074 * "#if 0" to "#if 1"
wdenka562e1b2005-01-09 18:21:42 +000075 * You will need a first stage bootloader then, e. g. colilo or a working BDM
76 * cable (Background Debug Mode)
77 *
78 * Setting #if 0: u-boot will start from flash and relocate itself to RAM
79 *
Wolfgang Denk14d0a022010-10-07 21:51:12 +020080 * Please do not forget to modify the setting of CONFIG_SYS_TEXT_BASE
wdenka562e1b2005-01-09 18:21:42 +000081 * in board/cobra5272/config.mk accordingly (#if 0: 0xffe00000; #if 1: 0x20000)
82 *
83 * ---
84 */
85
86#if 0
87#define CONFIG_MONITOR_IS_IN_RAM /* monitor is started from a preloader */
88#endif
89
90/* ---
91 * Configuration for environment
92 * Environment is embedded in u-boot in the second sector of the flash
93 * ---
94 */
95
96#ifndef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020097#define CONFIG_ENV_OFFSET 0x4000
98#define CONFIG_ENV_SECT_SIZE 0x2000
wdenka562e1b2005-01-09 18:21:42 +000099#else
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200100#define CONFIG_ENV_ADDR 0xffe04000
101#define CONFIG_ENV_SECT_SIZE 0x2000
wdenka562e1b2005-01-09 18:21:42 +0000102#endif
103
angelo@sysam.it5296cb12015-03-29 22:54:16 +0200104#define LDS_BOARD_TEXT \
Simon Glass0649cd02017-08-03 12:21:49 -0600105 . = DEFINED(env_offset) ? env_offset : .; \
106 env/embedded.o(.text);
Jon Loeliger37e4f242007-07-04 22:31:56 -0500107
108/*
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500109 * BOOTP options
110 */
111#define CONFIG_BOOTP_BOOTFILESIZE
112#define CONFIG_BOOTP_BOOTPATH
113#define CONFIG_BOOTP_GATEWAY
114#define CONFIG_BOOTP_HOSTNAME
115
Jon Loeliger80ff4f92007-07-10 09:29:01 -0500116/*
Jon Loeliger37e4f242007-07-04 22:31:56 -0500117 * Command line configuration.
wdenka562e1b2005-01-09 18:21:42 +0000118 */
wdenka562e1b2005-01-09 18:21:42 +0000119
TsiChungLiew67064242007-08-15 19:41:06 -0500120#ifdef CONFIG_MCFFEC
TsiChungLiew67064242007-08-15 19:41:06 -0500121# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -0500122# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200123# define CONFIG_SYS_DISCOVER_PHY
124# define CONFIG_SYS_RX_ETH_BUFFER 8
125# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew67064242007-08-15 19:41:06 -0500126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127# define CONFIG_SYS_FEC0_PINMUX 0
128# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200129# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
131# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew67064242007-08-15 19:41:06 -0500132# define FECDUPLEX FULL
133# define FECSPEED _100BASET
134# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
136# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew67064242007-08-15 19:41:06 -0500137# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew67064242007-08-15 19:41:06 -0500139#endif
wdenka562e1b2005-01-09 18:21:42 +0000140
141/*
142 *-----------------------------------------------------------------------------
143 * Define user parameters that have to be customized most likely
144 *-----------------------------------------------------------------------------
145 */
146
147/*AUTOBOOT settings - booting images automatically by u-boot after power on*/
148
wdenka562e1b2005-01-09 18:21:42 +0000149/* The following settings will be contained in the environment block ; if you
150want to use a neutral environment all those settings can be manually set in
151u-boot: 'set' command */
152
153#if 0
154
155#define CONFIG_BOOTCOMMAND "bootm 0xffe80000" /*Autoboto command, please
156enter a valid image address in flash */
157
wdenka562e1b2005-01-09 18:21:42 +0000158/* User network settings */
159
wdenka562e1b2005-01-09 18:21:42 +0000160#define CONFIG_IPADDR 192.168.100.2 /* default board IP address */
161#define CONFIG_SERVERIP 192.168.100.1 /* default tftp server IP address */
162
163#endif
164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_LOAD_ADDR 0x20000 /*Defines default RAM address
wdenka562e1b2005-01-09 18:21:42 +0000166from which user programs will be started */
167
168/*---*/
169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenka562e1b2005-01-09 18:21:42 +0000171
wdenka562e1b2005-01-09 18:21:42 +0000172/*
173 *-----------------------------------------------------------------------------
174 * End of user parameters to be customized
175 *-----------------------------------------------------------------------------
176 */
177
178/* ---
179 * Defines memory range for test
180 * ---
181 */
182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MEMTEST_START 0x400
184#define CONFIG_SYS_MEMTEST_END 0x380000
wdenka562e1b2005-01-09 18:21:42 +0000185
186/* ---
187 * Low Level Configuration Settings
188 * (address mappings, register initial values, etc.)
189 * You should know what you are doing if you make changes here.
190 * ---
191 */
192
193/* ---
194 * Base register address
195 * ---
196 */
197
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
wdenka562e1b2005-01-09 18:21:42 +0000199
200/* ---
201 * System Conf. Reg. & System Protection Reg.
202 * ---
203 */
204
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_SCR 0x0003
206#define CONFIG_SYS_SPR 0xffff
wdenka562e1b2005-01-09 18:21:42 +0000207
208/* ---
209 * Ethernet settings
210 * ---
211 */
212
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_DISCOVER_PHY
214#define CONFIG_SYS_ENET_BD_BASE 0x780000
wdenka562e1b2005-01-09 18:21:42 +0000215
216/*-----------------------------------------------------------------------
217 * Definitions for initial stack pointer and data area (in internal SRAM)
218 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200220#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200221#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200222#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenka562e1b2005-01-09 18:21:42 +0000223
224/*-----------------------------------------------------------------------
225 * Start addresses for the final memory configuration
226 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenka562e1b2005-01-09 18:21:42 +0000228 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenka562e1b2005-01-09 18:21:42 +0000230
231/*
232 *-------------------------------------------------------------------------
233 * RAM SIZE (is defined above)
234 *-----------------------------------------------------------------------
235 */
236
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200237/* #define CONFIG_SYS_SDRAM_SIZE 16 */
wdenka562e1b2005-01-09 18:21:42 +0000238
239/*
240 *-----------------------------------------------------------------------
241 */
242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_FLASH_BASE 0xffe00000
wdenka562e1b2005-01-09 18:21:42 +0000244
245#ifdef CONFIG_MONITOR_IS_IN_RAM
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define CONFIG_SYS_MONITOR_BASE 0x20000
wdenka562e1b2005-01-09 18:21:42 +0000247#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
wdenka562e1b2005-01-09 18:21:42 +0000249#endif
250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_MONITOR_LEN 0x20000
252#define CONFIG_SYS_MALLOC_LEN (256 << 10)
253#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenka562e1b2005-01-09 18:21:42 +0000254
255/*
256 * For booting Linux, the board info and command line data
257 * have to be in the first 8 MB of memory, since this is
258 * the maximum mapped by the Linux kernel during initialization ??
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenka562e1b2005-01-09 18:21:42 +0000261
262/*-----------------------------------------------------------------------
263 * FLASH organization
264 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
266#define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */
267#define CONFIG_SYS_FLASH_ERASE_TOUT 1000 /* flash timeout */
wdenka562e1b2005-01-09 18:21:42 +0000268
269/*-----------------------------------------------------------------------
270 * Cache Configuration
271 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200272#define CONFIG_SYS_CACHELINE_SIZE 16
wdenka562e1b2005-01-09 18:21:42 +0000273
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600274#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200275 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600276#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200277 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600278#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
279#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
280 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
281 CF_ACR_EN | CF_ACR_SM_ALL)
282#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
283 CF_CACR_DISD | CF_CACR_INVI | \
284 CF_CACR_CEIB | CF_CACR_DCM | \
285 CF_CACR_EUSP)
286
wdenka562e1b2005-01-09 18:21:42 +0000287/*-----------------------------------------------------------------------
288 * Memory bank definitions
289 *
290 * Please refer also to Motorola Coldfire user manual - Chapter XXX
291 * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
294#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
wdenka562e1b2005-01-09 18:21:42 +0000295
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200296#define CONFIG_SYS_BR1_PRELIM 0
297#define CONFIG_SYS_OR1_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000298
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_BR2_PRELIM 0
300#define CONFIG_SYS_OR2_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000301
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_BR3_PRELIM 0
303#define CONFIG_SYS_OR3_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_BR4_PRELIM 0
306#define CONFIG_SYS_OR4_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_BR5_PRELIM 0
309#define CONFIG_SYS_OR5_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_BR6_PRELIM 0
312#define CONFIG_SYS_OR6_PRELIM 0
wdenka562e1b2005-01-09 18:21:42 +0000313
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_BR7_PRELIM 0x00000701
315#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
wdenka562e1b2005-01-09 18:21:42 +0000316
317/*-----------------------------------------------------------------------
318 * LED config
319 */
320#define LED_STAT_0 0xffff /*all LEDs off*/
321#define LED_STAT_1 0xfffe
322#define LED_STAT_2 0xfffd
323#define LED_STAT_3 0xfffb
324#define LED_STAT_4 0xfff7
325#define LED_STAT_5 0xffef
326#define LED_STAT_6 0xffdf
327#define LED_STAT_7 0xff00 /*all LEDs on*/
328
329/*-----------------------------------------------------------------------
330 * Port configuration (GPIO)
331 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200332#define CONFIG_SYS_PACNT 0x00000000 /* PortA control reg.: All pins are external
wdenka562e1b2005-01-09 18:21:42 +0000333GPIO*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_PADDR 0x00FF /* PortA direction reg.: PA7 to PA0 are outputs
wdenka562e1b2005-01-09 18:21:42 +0000335(1^=output, 0^=input) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_PADAT LED_STAT_0 /* PortA value reg.: Turn all LED off */
337#define CONFIG_SYS_PBCNT 0x55554155 /* PortB control reg.: Ethernet/UART
wdenka562e1b2005-01-09 18:21:42 +0000338configuration */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#define CONFIG_SYS_PBDDR 0x0000 /* PortB direction: All pins configured as inputs */
340#define CONFIG_SYS_PBDAT 0x0000 /* PortB value reg. */
341#define CONFIG_SYS_PDCNT 0x00000000 /* PortD control reg. */
wdenka562e1b2005-01-09 18:21:42 +0000342
343#endif /* _CONFIG_COBRA5272_H */